Example designs for communicating two Altera boards

[Altera_Forum]

I am looking for example designs or tutorials showing how to communicate two Altera boards using simple protocols. The purpose is to see how the two devices interact by transmitting data back and forth and to check the transmission somehow. I am using two Altera Transceiver Signal Integrity Development Kit, Stratix IV GT (EP4S100G2F40I1) boards. 

 Please help to advice if anyone knows such tutorials and examples. Also, any suggestions are highly appreciated.   Thanks.

[Altera_Forum]

--- Quote Start ---   Anyway, we are going to replace the OS soon. Probably, we will use Redhat Enterprise.   --- Quote End ---  That should resolve the issue.    --- Quote Start ---   Regarding the socket programming you mentioned before, I have no experience on this, if you can tell me some tools and are they OS dependent? For example if they work well in Windows?   --- Quote End ---  Berkeley sockets is the 'classic' Unix sockets programming interface. Windows has a slightly different API, but much the same sequence. You can use Cygwin under Windows and use the sockets API. You can also use middleware that makes the interfaces identical. For example, I have used the ACE C++ classes under both Windows and Linux. There are a couple of books on the subject:  http://www.amazon.com/network-programming-volume-mastering-complexity/dp/0201604647/ref=sr_1_1?ie=utf8&qid=1333827005&sr=8-1  http://www.amazon.com/network-programming-volume-systematic-frameworks/dp/0201795256/ref=sr_1_2?ie=utf8&qid=1333827005&sr=8-2  http://www.amazon.com/the-ace-programmers-guide-programming/dp/0201699710/ref=sr_1_3?ie=utf8&qid=1333827005&sr=8-3  You could also look at the boost C++ library. I believe they have some OS abstractions in the library now.  Cheers, Dave

[Altera_Forum]

Dear Dave, 

 Thank you a lot indeed. Your explanations give me a better understanding about what I need to do. By now, it is enough for an overview. I am going to learn and implement my project step by step. And hopefully whenever I get stuck on the way, I will be receiving your useful advice.   Best, PLMT.

[Altera_Forum]

--- Quote Start ---  If one board uses a 156.25MHz reference that is actually a few kHz high, and the other board uses a reference that is a few kHz low, then one board will send data to the other faster than ideal. The clock-and-data recovery (CDR) in the receiver will track the higher frequency, however, if you use a FIFO to cross clock domains between the recovered clock and the local clock, you will eventually get a FIFO overrun (or underrun in the case of a slower transmitter). Protocols like 10G take care of this by having protocol codes that can be added or deleted. If you are implementing FPGA-to-FPGA communications, then the system becomes simpler if you use a synchronous reference. You can implement this reference using an external synthesizer and send a copy of the signal to each board, or you can use one of your boards as the clock source and the other can receive a clock from the first, and use it for clocking its receiver logic.  --- Quote End ---    Dear Dave,   How can I implement the synchronous reference clock? If you can provide some more details regarding the external synthesizer such as examples, materials,...I am thinking this is the problem for the board-to-board communication I am encountering now.  Thanks

[Altera_Forum]

--- Quote Start ---   How can I implement the synchronous reference clock?   --- Quote End ---  Look at your board schematics.  1) Is there an clock output on an SMA connector? Eg., from an FPGA clock pin or from an on-board oscillator fanout buffer?   2) Is there a clock input on an SMA connector?  3) Connect board#1 -> board# 2 with an SMA cable from the clock output SMA to the clock input SMA.  4) The design on the board#1 (with the SMA clock output) should use an FPGA pin with the same clock as the output clock. The design on the board#2 (with the SMA clock input) should use the SMA input clock as the reference. Now both boards are synchronous.  5) The high-speed transceiver links will start in lock-to-reference, and then transition to lock-to-data mode. Since the data source and sink PLLs are locked to the same reference, you won't see any clock drift.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Look at your board schematics.  1) Is there an clock output on an SMA connector? Eg., from an FPGA clock pin or from an on-board oscillator fanout buffer?   2) Is there a clock input on an SMA connector?  3) Connect board#1 -> board# 2 with an SMA cable from the clock output SMA to the clock input SMA.  4) The design on the board#1 (with the SMA clock output) should use an FPGA pin with the same clock as the output clock. The design on the board#2 (with the SMA clock input) should use the SMA input clock as the reference. Now both boards are synchronous.  5) The high-speed transceiver links will start in lock-to-reference, and then transition to lock-to-data mode. Since the data source and sink PLLs are locked to the same reference, you won't see any clock drift.  --- Quote End ---    Great advice! exactly what I am looking for. I think this will really helps. I will try this weekend and update the result then.  Thanks a lot.

[Altera_Forum]

Dear Dave, 

 I have tried to feed the two designs with only one source of clock. But it seems like the RX design did not get a proper input clock from the TX. I tried to test internal loopback at RX and had this error msg when started the monitor process:  error: This transaction did not complete in 60 seconds. System Console is giving up.  while executing "master_write_32 {/devices/EP4S(100G2|40G2)@1#USB-0/(link)/JTAG/(110:132 v1# 0)/phy_0/master} {0x1000004} {0x00000001}"  while executing "master_write_32 $port_id $address $wdata"  (procedure "reg_write" line 9)  invoked from within "reg_write $GEN_BASE_ADDR $GEN_RANDOMLENGTH 0x00000001 "  (procedure "SETGEN_LENGTHRANDOM" line 5)  invoked from within "SETGEN_LENGTHRANDOM"  (procedure "CONFIG_BURST" line 2)  invoked from within "CONFIG_BURST $bursttype $burstsize $pkttype $pktsize "  (procedure "CONFIG_TRAFFIC" line 14)  invoked from within "CONFIG_TRAFFIC $BURST_TYPE $burst_size $PACKET_TYPE $PACKET_SIZE $MAC_SRC_ADDRESS $MAC_DST_ADDRESS"  (procedure "TEST_ALTPMA" line 7)  invoked from within "TEST_ALTPMA $TEST_BURST"  (procedure "TEST" line 42)  invoked from within "TEST ALTPMA 100 1"  Do you have an idea of where the error comes from? I just can think that the RX design does not have the synced clock. (Well, the design works well if I use the 100 clock from local generator in board)  Briefly, the design needs two input clocks, one is a 644.53 MHz reference clock for 10 Gbps Eth component (that provides a 156.25 MHz clock for PCS block), and the other is a 100 MHz synchronous clock that is the common clock for all the components including System controller, Eth10g, Traffic controller (=traffic generator+traffic monitor).  I checked the reference manual and there is a differential SMA clock output (pin J16, J17) from FPGA (pin K34, J34) and a differential SMA clock input (pin J14, J15) to FPGA core pin (AV22, AW22). Therefore, I use a pair of SMA cables to connect (J16, J17) in TX board to (J14, J15) in RX board and assign the 100 input clock in RX design to (AV22, AW22). That way, the RX should have the synced clock with TX. What else I should check? If I need to provide the same reference clock for both TX and Eth10g? I did not do this because the board has only differential SMA clock input to FPGA transceiver but not output one.  By the way, I don't really understand the purpose of the word "differential", namely, both clock and transceiver channel have positive and negative components. Can I just use only either positive or negative when I assign pins for designs? Please help to answer.  This is the reference manual for me board: http://www.altera.com/literature/manual/rm_sivgt_si_dev_board.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=stratix%20iv%20gt%20signal%20integrity    --- Quote Start ---  5) The high-speed transceiver links will start in lock-to-reference, and then transition to lock-to-data mode. Since the data source and sink PLLs are locked to the same reference, you won't see any clock drift.  --- Quote End ---    Regarding this, did you mean the RX Eth10 component first use the local reference clock and then it extracts clock from receiving data? And how can I check or implement this?   Thank you very much.

[Altera_Forum]

--- Quote Start ---   error: This transaction did not complete in 60 seconds. System Console is giving up. while executing ...   --- Quote End ---  If you haven't taken the time to understand the SystemConsole code or the design it is controlling, then you have no way of understanding why its failing. This is why I told you earlier, you have to understand the design, and then create your own.  If you create a simulation of your system with two boards, you can check whether the first design is outputting a clock to the second design. If you don't have a simulation, then use an oscilloscope.  No one on this forum will be able to answer questions about software or hardware designs that you are asking questions about when you have not taken the time to understand them. As soon as you understand them, you'll have no need to ask questions.   Problem solving comes with experience, don't give up the first time something does not work, rather, take it as a challenge and develop problem solving skills.  For example, even without an oscilloscope, you have Modelsim for simulation and SignalTap II for hardware debugging. Take the time to create a Modelsim simulation, and then test the hardware. Use SignalTap II to figure out where you have gone wrong, and keep attacking the problems until you solve them.  I know the procedure for synchronizing two boards works, as I use it all the time, to synchronize a pair of Stratix IV GX development kits. I saw plenty of SMA connectors on the Stratix IV GT SI kit, get out your oscilloscope and start checking there are clocks on the SMA connectors you expect to have clocks.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  Problem solving comes with experience, don't give up the first time something does not work, rather, take it as a challenge and develop problem solving skills.  --- Quote End ---    Thank you very much for your advice. I will try more to solve out the problem.