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Altera_Forum
Honored Contributor I
776 Views

External Memory without BGA?

Hi, 

 

i need external memory for a MAX10 FPGA (10M50SCE144I7G). 

I am not able to solder BGA packages. 

 

Is it possible, to use a SDRAM with this device? 

Only the BGA packages have a memory interface: 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/max-10/ug_m10_emi.pdf (page 7) 

 

Can I do it without a dedicated memory interface? 

It´s no problem if it is slow, I only need the memory for a NIOSII. 

I don´t need high performance, but a huge memory. 

 

I´d like to use this DDR SDRAM: 

http://docs-europe.electrocomponents.com/webdocs/13f3/0900766b813f3609.pdf 

 

Which IP-core memory controller is suitable for this memory? 

I can´t find something about DDR ram, the Altera Documents cover only DDR2 and DDR3. 

 

Regards 

Olaf
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6 Replies
Altera_Forum
Honored Contributor I
25 Views

I'm afraid it doesn't tell you what you want to hear but see this Support Solution - "does the max 10 uniphy ip support sdr sdram or sram? (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09282015_250.html)". 

 

If you must use MAX 10 you'll have to consider using BGAs. There are plenty of Altera references to copy: 

Have a look at Altera's "max 10 fpga 10m50 evaluation kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10m50-evaluation.html)". This features a LPDDR2 memory device. 

Also, the "max 10 fpga development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/max-10-fpga-development-kit.html)" which features a DDR3 device. 

 

If you must use SDRAM then search Altera for "sdr sdram ip (https://www.altera.com/bin/search?q=sdr+sdram+ip&client=cq_www_frontend&output=xml_no_dtd&proxystyle...)". However, you will have to consider a different FPGA family, unless you wish to write the IP yourself. There's no reason you can't interface SDR SDRAM to MAX 10, it's simply that Altera's IP doesn't support that. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
25 Views

PS. Scrap that... 

 

I've just run Qsys up as part of a MAX 10 project and it does offer you the option to add a SDR SDRAM to a Nios. It seems to run through Quartus quite happily too...
Altera_Forum
Honored Contributor I
25 Views

Hi, thank you very much! 

I´ll try that. 

 

And I don´t need a dedicatet memory interface for that? 

 

Greets 

Olaf
Altera_Forum
Honored Contributor I
25 Views

I'm guessing that if you don't use the built in hardware memory controller you will end up using lots of scarce FPGA resources in your relatively small MAX 10. I'd suggest copying exactly the layout of the DDR lines from a dev board and using a BGA based memory device(s). If you are soldering it yourself, I'd suggest getting a BGA soldering practice kit and some paste and heat gun and working with it before doing your FPGA board. Essentially, you bake the board before use to drive off water, then put down a dot of solder paste on each pad on the board, carefully position the BGA and use the heat gun. There are plenty of tutorials on YouTube to show you how.

Altera_Forum
Honored Contributor I
25 Views

Thank you, 

 

than I will use BGA, this will also give me the oppertunity to use CycloneV and DDR3 RAM. 

I think, i will let it assemble in China, i dont wanna scrap an expensive FPGA. 

 

Greets  

Olaf
Altera_Forum
Honored Contributor I
25 Views

Fine, but don't bite off more than you can chew. With a full on FPGA you also need to get multiple power rails powered up correctly and there's configuration to deal with too. Get a board or two with a simple CPLD designed and working before you tackle that big of a project.