External SRAM Timing Problems

Altera_Forum · ‎04-24-2009

Hi all,

I work on a task of porting NiosII Softcore processor, JTAG UART, SRAM, FLASH, ON-CHIP along with a Tri-State Bridge in Cyclone III(EP3C25F324C8).

I had the program compiled sucessfully and on running a simple Hello-World program it says the popular error

using cable "usb-blaster [usb-0]", device 1, instance 0x00

pausing target processor: ok

reading system id at address 0x08002f40: verified

initializing cpu cache (if present)

ok

downloading 05000000 ( 0%)

downloaded 62kb in 1.0s (62.0kb/s)

verifying 05000000 ( 0%)

verify failed between address 0x5000000 and 0x500f79b

leaving target processor paused

But I am able to run a Hello_World program from on-chip memory.

Where am I going wrong?

Is it in the SRAM's Timing?

Should i do anything with Tsu and Tco requirements in the Assignments editor?

Many thanks...

Altera_Forum · ‎04-25-2009

In your SOPC_builder,you could find which device's address is include 0x5000000 and 0x500F79B,then you can surely about which device is going wrong.

[/B][/B]