Extracting .jic from cyclone III

[Altera_Forum]

Hi,  

 Does anybody know if it is possible at all to extract and copy/open/read/write a design from a .jic file already installed on a Cyclone III FPGA?  If yes, what are the ways to prevent or control it?  Can somebody suggest any literature on this topic?  Thanks in advance

[Altera_Forum]

someone could read out the SPI flash, clone your board, and duplicate your product 

 some families support encryption of the configuration file (Cyclone III not included, but Cyclone III LS included) which helps mitigate this sort of problem  alternatively you could develop your own basic key exchange type scheme where a CPLD or microcontroller generates a PN code and sends it over to the FPGA which is matching the PN codes. if the match is not made, the FPGA design breaks (maybe it disables an enable signal somewhere). reading the CPLD or uC will be significantly harder than reading a small flash

[Altera_Forum]

Thanks for the answer! 

 If the .jic is in a configuration EEPROM, instead of a flash, it still does not make a difference, right? My idea is that it can still be read, since it is memory. Please correct me if I'm wrong.  Then, is there any chance at all whatsoever to protect your design from being copied if you have a simple cyclone III, without using an external programming device (uC or CPLD) and a battery to keep it up?

[Altera_Forum]

yes, if its got traces on the board its fairly easy to read out. that's in contrast with something like a MAX V or uC that has on board configuration flash. its much more difficult to pull the data (but still possible) 

 no, not really. you might search the forum for similar topics and see if there were any other ideas proposed

[Altera_Forum]

To avoid someone stealing and cloning your CIII design, you need an external device. 

Please refer to this page on Altera website for a description of security issues: http://www.altera.com/devices/fpga/cyclone3/overview/security/cy3-security.html There are also a few white papers (e.g. WP-01111, WP-01033, WP-M2DSGN-01) which address this problem. I myself implemented the solution proposed in wp01033.

[Altera_Forum]

Thanks a lot guys!

[Altera_Forum]

--- Quote Start ---   I myself implemented the solution proposed in wp01033.  --- Quote End ---   What is Your opinion about this solution? Does it have any errors or performs fine?

[Altera_Forum]

--- Quote Start ---  What is Your opinion about this solution? Does it have any errors or performs fine?  --- Quote End ---   It performs fine. I copied and pasted in my design the hdl code provided by Altera and it worked immediately, without any effort.

[Altera_Forum]

--- Quote Start ---  It performs fine. I copied and pasted in my design the hdl code provided by Altera and it worked immediately, without any effort.  --- Quote End ---   Does that mean, that no DS28E01 datasheet study is needed? Just use DS28E01 as a "black box"? What about hdl code - is it published somewhere or needed to be requested at Altera under NDA?

[Altera_Forum]

--- Quote Start ---  Does that mean, that no DS28E01 datasheet study is needed? Just use DS28E01 as a "black box"?   --- Quote End ---   Definitely yes.  You need to read the datasheet in order to learn that you need a 2.2k pullup resistor between onewire signal (DS28E01 pin 2) and 3.3V supply: but now I have told you :cool:, so you should not need the datasheet at all. In the HDL code you only need to set your secure code key and possibly change the clock frequency.    --- Quote Start ---   What about hdl code - is it published somewhere or needed to be requested at Altera under NDA?   --- Quote End ---   Request at Altera.  IIRC they don't require a NDA. They simply ask you generic details about your target application.

[Altera_Forum]

--- Quote Start ---  It performs fine. I copied and pasted in my design the hdl code provided by Altera and it worked immediately, without any effort.  --- Quote End ---   Before that You had to program DS28E01 with secret code with the use of the same FPGA. Can that be done several times? How to check, that DS28E01 really got programmed?  In the "Cyclone III FPGA Design Security Solution Using SHA-1 with DS28E01 Reference Design User Guide" it is said, that "After the SHA-1 IFF module enables the user design, the block will be turned off to save power consumption." What is the form of the "Enable" signal? A constant high level even after the SHA-1 IFF module will be turned off or a pulse?

[Altera_Forum]

--- Quote Start ---  Before that You had to program DS28E01 with secret code with the use of the same FPGA. Can that be done several times?   --- Quote End ---   Yes. The code is rewritable    --- Quote Start ---   How to check, that DS28E01 really got programmed?   --- Quote End ---   You may use the "enabler" code and expose the enable signal in order to test its level after security check.    --- Quote Start ---   What is the form of the "Enable" signal? A constant high level even after the SHA-1 IFF module will be turned off or a pulse?  --- Quote End ---   If the security check is successfull, it goes high and keeps the level forever