Hello Intel forums
I have an Agilex 7 devkit that I'm working with. I'm still learning my way around the F-tile transceiver IPs and the Reference and System clocks PLL.
On the Agilex 7 devkit, refclks 8 & 9 on transceiver tile 12A are connected to the input of a SI5518 clock chip. I would like to make use of this connection to drive the SI5518. Can you tell me if the following are true:
- From what I understand, the connections of refclks 8 & 9 are restricted to the "out_cdrclk_i" ports of the Reference and System Clocks IP for that tile.
- I also understand that the "in_cdrclk_i" can only be connected to the "rx_cdr_divclk_link0" port of a transceiver IP on that tile.
- The frequency of "rx_cdr_divclk_link0" is given by the reference clock frequency divided by cdr_n_counter. In my case, this is 320MHz/12 = 26.666667 MHz. Assuming 1 & 2 are correct, I would need to configure the SI5518 to have this as the input frequency
Is "rx_cdr_divclk_link0" synchronized to the provided reference clock or to the clock recovered from the incoming data stream? To me, 'cdr' implies that it's related to the recovered clock, but I'm not sure if my understanding is correct.
Thank you for your assistance.
Kind Regards,
Sam
