FCS(crc32) ethernet on cycloneII?

Altera_Forum · ‎06-16-2010

I have tested free internet codes for FCS ethernet, but it don't work.

What's wrong? HELP me please gurus!

CRC32 FOR 1 FIXED BYTE(0X1A)

rstn->always 0

enable->always 1

init->1 time 1 short pulse for init crc module

DataIN->0x1A

CRC generated from module-> 0x2D93B212

CORRECT CRC->0xf716602f

internet code:

module crc32_data8 (

clk,

rstn,

enable,

init,

d, //datain

crc, //crc

match //set if crc=0

);

input clk;

input rstn;

input enable;

input init;

input [7:0] d;

output [31:0] crc;

output match;

　

wire [31:0] c;

wire [31:0] newcrc;

reg [31:0] crc;

reg match;

　

always @ (posedge clk )

begin

if(rstn) begin

crc [31:0] <= {32{1'b1}};

match <= 1'b0;

end

else

begin

if(init) begin

crc [31:0] <= {32{1'b1}};

match <= 1'b0;

end

else

if(enable)

begin

crc <= newcrc;

if (crc==32'd0) match<=1'b1; else match<=1'b0;

end

　

assign c = crc;

assign newcrc[0] = d[6] ^ d[0] ^ c[30] ^ c[24];

assign newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[25] ^ c[24];

assign newcrc[2] = d[7] ^ d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[26] ^ c[25] ^ c[24];

assign newcrc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[31] ^ c[27] ^ c[26] ^ c[25];

assign newcrc[4] = d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[30] ^ c[28] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[5] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[29] ^ c[28] ^ c[27] ^ c[25] ^ c[24];

assign newcrc[6] = d[7] ^ d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[31] ^ c[30] ^ c[29] ^ c[28] ^ c[26] ^ c[25];

assign newcrc[7] = d[7] ^ d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[31] ^ c[29] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[8] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[28] ^ c[27] ^ c[25] ^ c[24] ^ c[0];

assign newcrc[9] = d[5] ^ d[4] ^ d[2] ^ d[1] ^ c[29] ^ c[28] ^ c[26] ^ c[25] ^ c[1];

assign newcrc[10] = d[5] ^ d[3] ^ d[2] ^ d[0] ^ c[2] ^ c[29] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[11] = d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[3] ^ c[28] ^ c[27] ^ c[25] ^ c[24];

assign newcrc[12] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[4] ^ c[30] ^ c[29] ^ c[28] ^ c[26] ^ c[25] ^ c[24];

assign newcrc[13] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[5] ^ c[31] ^ c[30] ^ c[29] ^ c[27] ^ c[26] ^ c[25];

assign newcrc[14] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ c[6] ^ c[31] ^ c[30] ^ c[28] ^ c[27] ^ c[26];

assign newcrc[15] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ c[7] ^ c[31] ^ c[29] ^ c[28] ^ c[27];

assign newcrc[16] = d[5] ^ d[4] ^ d[0] ^ c[8] ^ c[29] ^ c[28] ^ c[24];

assign newcrc[17] = d[6] ^ d[5] ^ d[1] ^ c[9] ^ c[30] ^ c[29] ^ c[25];

assign newcrc[18] = d[7] ^ d[6] ^ d[2] ^ c[31] ^ c[30] ^ c[26] ^ c[10];

assign newcrc[19] = d[7] ^ d[3] ^ c[31] ^ c[27] ^ c[11];

assign newcrc[20] = d[4] ^ c[28] ^ c[12];

assign newcrc[21] = d[5] ^ c[29] ^ c[13];

assign newcrc[22] = d[0] ^ c[24] ^ c[14];

assign newcrc[23] = d[6] ^ d[1] ^ d[0] ^ c[30] ^ c[25] ^ c[24] ^ c[15];

assign newcrc[24] = d[7] ^ d[2] ^ d[1] ^ c[31] ^ c[26] ^ c[25] ^ c[16];

assign newcrc[25] = d[3] ^ d[2] ^ c[27] ^ c[26] ^ c[17];

assign newcrc[26] = d[6] ^ d[4] ^ d[3] ^ d[0] ^ c[30] ^ c[28] ^ c[27] ^ c[24] ^ c[18];

assign newcrc[27] = d[7] ^ d[5] ^ d[4] ^ d[1] ^ c[31] ^ c[29] ^ c[28] ^ c[25] ^ c[19];

assign newcrc[28] = d[6] ^ d[5] ^ d[2] ^ c[30] ^ c[29] ^ c[26] ^ c[20];

assign newcrc[29] = d[7] ^ d[6] ^ d[3] ^ c[31] ^ c[30] ^ c[27] ^ c[21];

assign newcrc[30] = d[7] ^ d[4] ^ c[31] ^ c[28] ^ c[22];

assign newcrc[31] = d[5] ^ c[29] ^ c[23];

endmodule

Altera_Forum · ‎06-16-2010

Try:

inverting the input

inverting the output(this one is usually obvious)

reversing the word order in

reversing the word order out

All combinations of that. I had a similar situation where a CRC I had was supposed to match that of a "black-box" CRC. What a pain. On top of it all there was a typo in one of the equations so it used the wrong bit. It was a week of my life I'd love to get back. Bottom line is be rigorous in checking every combination. (The final one was flipping the order of 8-bit boundaries, but I think that was unique to my case...)

Altera_Forum · ‎06-17-2010

the right code (it needs only invert the outputs with the module myblkinv2):

TNX to your help

module crc32_data8 (

clk,

rstn,

enable,

init,

d, //datain

crc, //crc

match //set if crc=0

);

input clk;

input rstn;

input enable;

input init;

input [7:0] d;

output [31:0] crc;

output match;

wire [31:0] c;

wire [31:0] newcrc;

reg [31:0] crc;

reg match;

always @ (posedge clk )

begin

if(rstn) begin

crc [31:0] <= {32{1'b1}};

match <= 1'b0;

end

else

begin

if(init) begin

crc [31:0] <= {32{1'b1}};

match <= 1'b0;

end

else

if(enable)

begin

crc <= newcrc;

if (crc==32'd0) match<=1'b1; else match<=1'b0;

end

assign c = crc;

assign newcrc[0] = d[7] ^ d[1] ^ c[30] ^ c[24];

assign newcrc[1] = d[7] ^ d[6] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[25] ^ c[24];

assign newcrc[2] = d[7] ^ d[6] ^ d[5] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[26] ^ c[25] ^ c[24];

assign newcrc[3] = d[6] ^ d[5] ^ d[4] ^ d[0] ^ c[31] ^ c[27] ^ c[26] ^ c[25];

assign newcrc[4] = d[7] ^ d[5] ^ d[4] ^ d[3] ^ d[1] ^ c[30] ^ c[28] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[5] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[29] ^ c[28] ^ c[27] ^ c[25] ^ c[24];

assign newcrc[6] = d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[29] ^ c[28] ^ c[26] ^ c[25];

assign newcrc[7] = d[7] ^ d[5] ^ d[4] ^ d[2] ^ d[0] ^ c[31] ^ c[29] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[8] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ c[28] ^ c[27] ^ c[25] ^ c[24] ^ c[0];

assign newcrc[9] = d[6] ^ d[5] ^ d[3] ^ d[2] ^ c[29] ^ c[28] ^ c[26] ^ c[25] ^ c[1];

assign newcrc[10] = d[7] ^ d[5] ^ d[4] ^ d[2] ^ c[2] ^ c[29] ^ c[27] ^ c[26] ^ c[24];

assign newcrc[11] = d[7] ^ d[6] ^ d[4] ^ d[3] ^ c[3] ^ c[28] ^ c[27] ^ c[25] ^ c[24];

assign newcrc[12] = d[7] ^ d[6] ^ d[5] ^ d[3] ^ d[2] ^ d[1] ^ c[4] ^ c[30] ^ c[29] ^ c[28] ^ c[26] ^ c[25] ^ c[24];

assign newcrc[13] = d[6] ^ d[5] ^ d[4] ^ d[2] ^ d[1] ^ d[0] ^ c[5] ^ c[31] ^ c[30] ^ c[29] ^ c[27] ^ c[26] ^ c[25];

assign newcrc[14] = d[5] ^ d[4] ^ d[3] ^ d[1] ^ d[0] ^ c[6] ^ c[31] ^ c[30] ^ c[28] ^ c[27] ^ c[26];

assign newcrc[15] = d[4] ^ d[3] ^ d[2] ^ d[0] ^ c[7] ^ c[31] ^ c[29] ^ c[28] ^ c[27];

assign newcrc[16] = d[7] ^ d[3] ^ d[2] ^ c[8] ^ c[29] ^ c[28] ^ c[24];

assign newcrc[17] = d[6] ^ d[2] ^ d[1] ^ c[9] ^ c[30] ^ c[29] ^ c[25];

assign newcrc[18] = d[5] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[26] ^ c[10];

assign newcrc[19] = d[4] ^ d[0] ^ c[31] ^ c[27] ^ c[11];

assign newcrc[20] = d[3] ^ c[28] ^ c[12];

assign newcrc[21] = d[2] ^ c[29] ^ c[13];

assign newcrc[22] = d[7] ^ c[24] ^ c[14];

assign newcrc[23] = d[7] ^ d[6] ^ d[1] ^ c[30] ^ c[25] ^ c[24] ^ c[15];

assign newcrc[24] = d[6] ^ d[5] ^ d[0] ^ c[31] ^ c[26] ^ c[25] ^ c[16];

assign newcrc[25] = d[5] ^ d[4] ^ c[27] ^ c[26] ^ c[17];

assign newcrc[26] = d[7] ^ d[4] ^ d[3] ^ d[1] ^ c[30] ^ c[28] ^ c[27] ^ c[24] ^ c[18];

assign newcrc[27] = d[6] ^ d[3] ^ d[2] ^ d[0] ^ c[31] ^ c[29] ^ c[28] ^ c[25] ^ c[19];

assign newcrc[28] = d[5] ^ d[2] ^ d[1] ^ c[30] ^ c[29] ^ c[26] ^ c[20];

assign newcrc[29] = d[4] ^ d[1] ^ d[0] ^ c[31] ^ c[30] ^ c[27] ^ c[21];

assign newcrc[30] = d[3] ^ d[0] ^ c[31] ^ c[28] ^ c[22];

assign newcrc[31] = d[2] ^ c[29] ^ c[23];

endmodule

module myblkinv2(in,out);

input[31:0] in;

wire[31:0] out;

output[31:0]out;

assign out[31]=~in[0];

assign out[30]=~in[1];

assign out[29]=~in[2];

assign out[28]=~in[3];

assign out[27]=~in[4];

assign out[26]=~in[5];

assign out[25]=~in[6];

assign out[24]=~in[7];

assign out[23]=~in[8];

assign out[22]=~in[9];

assign out[21]=~in[10];

assign out[20]=~in[11];

assign out[19]=~in[12];

assign out[18]=~in[13];

assign out[17]=~in[14];

assign out[16]=~in[15];

assign out[15]=~in[16];

assign out[14]=~in[17];

assign out[13]=~in[18];

assign out[12]=~in[19];

assign out[11]=~in[20];

assign out[10]=~in[21];

assign out[9]=~in[22];

assign out[8]=~in[23];

assign out[7]=~in[24];

assign out[6]=~in[25];

assign out[5]=~in[26];

assign out[4]=~in[27];

assign out[3]=~in[28];

assign out[2]=~in[29];

assign out[1]=~in[30];

assign out[0]=~in[31];

endmodule