FFT Megacore Timing Simulation

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

FFT Megacore Timing Simulation

842 Views

Hi,

I am simulating a circuit that uses the FFT Megacore function. When the simulatoin is functional, it works fine. However, it only produces the first output (which is correct) when tested using the Timing mode. All the other outputs are 0.

I have checked the input and it seems like the input is being fed into the block correctly. The design also compiles without any critical warnings on timing. Does anyone have any idea? Any feedback is appreciated.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.