FFT timing?

[Altera_Forum]

Hi I need to perform a 256 point FFT operation. I use the SOP and EOP signals to indicate the start and end of operation with sink_ready always high. My simulation suggests that the input data is perfect yet the output is incorrect. The user guide specifies that the data must change on the rising edge of the clock. is this how one feeds data into the IP core. Since the input data is correct I can only assume that the problem could be with timing. How sensitive is the IP core to timing and clock skews? Has anyone ever encountered a similar problem where one gives the core the correct input but it either samples it incorreclty or ingnores some inputs?

[Altera_Forum]

Altera's FFT IP Core can achieve operating frequencies upon 333 MHz (Stratix II Device). Are you using a higher frequency on your device? 

 Did you look the altera examples?  Firstable try this, in order to understand the Avalon Interface.  This example explains the use of the FFT core to perform an OFDM modulation  http://www.altera.com/support/examples/download/ofdm_modulation_v72.zip

[Altera_Forum]

Try to use a much lower speed in order to understand if it is a timing problem. What FPGA are you using in your design?

[Altera_Forum]

Thank you for your recommendation. I am using a Stratix 2 device and I am only operating at 1 Mhz. Am I correct in saying that when using the avalon interface, the source feeding the sink interface should not use the same clock. I.e the source should update the data, or assert the SOP signal and some time later when the signal has settled,the sink interface running off a different clock must sample the values, or am I missing the point?

[Altera_Forum]

How can you be sure that your output is wrong? Are you comparing your output with the result of a Matlab simulation? 

In this case you have to be sure that your Matlab simulation is using the same numerical format of the Altera FFT implementation, i.e. resolution and/or real/integer format. At 1MHz you should not experience any timing problems, so the error could be hidden somewhere else.

[Altera_Forum]

I know that the output is incorrect because I reverse the process of the original FFT operation with an IFFT operation.I have experimented more ans there seems to be a correlation between when the systems does not work and when if functions. If I remove/add ouput pins from the design it changes the response of the system? I need the output pins to view the results of the simulation but by remiving and adding them I am changing the system. Should I make the output pins virtual, as they are currently only unassigned?

[Altera_Forum]

Is it possible that by adding output pins to a specific design can change the timing of the system and hence the system will produce incorrect output. I seem to have this problem if I remove or add output pins on the bus feeding data to the FFT Megacore function the timing simulation yields different results. Why would this happen?

[Altera_Forum]

I don't think that operating at 1MHz you should experiment timing violations. Does the timing analyzer give you errors?

[Altera_Forum]

In reference to your second comment. If you are crossing clock domains from source->sink you are going to need a dcfifo or something like that (your own synchronization scheme) in order to synch up the two different clocks and I/O signals.