FIR Compiler II multichannel operation

[Altera_Forum]

Hi all. 

 I'm using FIR compiler II megafunction to create a block with the following parameters:  Decimation filter this N = 2; Number of channels : 11; Clock frequency : 50 MHz; Input sample rate : 0.12 MHz;  I have got new input ports: ast_sink_sop and ast_sink_eop.  Sometimes i want to send data only to the channel number 1 and don't use other channels. How can I do it?

[Altera_Forum]

if you don't need any channel just ignore it. its input becomes irrelevant and you will discard its output. You need however (I believe) keep valid same for all cases since the core expects 11 valid data per its cycle.

[Altera_Forum]

I have a few cases: 

 1. Use all channels : Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel EoP is '1' only then send data of 10 channel  2. Use only 3 channels Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel EoP is '1' only then send data of 2 channel  Am I right?  3. Use only 1 channel Valid is '1' all 11 cycles SoP is '1' only then send data of 0 channel When I should use EoP?

[Altera_Forum]

your valid is ok. 

your SOP,EOP what are these? I assume some start/end of some frames. If you are filtering then I don't know what frames mean here. Can you explain it please?

[Altera_Forum]

In my filter Input sample rate much less than Clock frequency, thats why all 11 channels can pass through 1 wire. 

Filter characteristics: PhysChanIn 1, PhysChanOut 1, ChansPerPhyIn 12, ChansPerPhyOut 12, OutputFullBitWidth 58, Bankcount 1, CoefBitWidth 20  In this case we have Start of packet and End of packet wires. (http://www.altera.com/literature/ug/ug_fir_compiler_ii.pdf Table 4–2 page 4–23)  Better picture of how it works is Figure 4–5.

[Altera_Forum]

FIR Compiler II's architecture is such that it always expects the same input pattern. So if you've created an 11-channel FIR filter but are only interested in 1 channel then you will need to pad the inputs with 10 dummy samples and then just ignore the corresponding outputs. Fairly certain EOP should always be asserted on the 11th channel.

[Altera_Forum]

--- Quote Start ---  In my filter Input sample rate much less than Clock frequency, thats why all 11 channels can pass through 1 wire. Filter characteristics: PhysChanIn 1, PhysChanOut 1, ChansPerPhyIn 12, ChansPerPhyOut 12, OutputFullBitWidth 58, Bankcount 1, CoefBitWidth 20  In this case we have Start of packet and End of packet wires. (http://www.altera.com/literature/ug/ug_fir_compiler_ii.pdf Table 4–2 page 4–23)  Better picture of how it works is Figure 4–5.  --- Quote End ---    I am used to dspBuilder fir design and in such cases no sop or eop exists as the fir core depends on valid for counting channels thus it will just count on valid from 0 to 10 for 11 channels and at next valid the count resets to 0 and so on.  It looks like fir compiler you are using needs valid as well as sop/eop as you know.  I believe since your design expects 11 channels then this is fixed and so sop/eop must be fixed irrespective of channels actually used. It will be safer to assume 11 channels and discard those you don't need.  but I could be wrong if your design can actually accommodate to any channels from 1 to 11 though it is set to 11.

[Altera_Forum]

Thanks all of you. 

 So, valid and sop/eop signals: valid high - all 11 cycles sop high - only 1 cycle eop high - only 11 cycle. Is this true?  And what about dummy samples? I think that i can't send dummy samples, because this will fake results.  It seems that there is no solution of this problem.

[Altera_Forum]

--- Quote Start ---  Thanks all of you.  So, valid and sop/eop signals: valid high - all 11 cycles sop high - only 1 cycle eop high - only 11 cycle. Is this true?  And what about dummy samples? I think that i can't send dummy samples, because this will fake results.  It seems that there is no solution of this problem.  --- Quote End ---    looks ok to me.  dummy input is not really needed, just ignore those inputs whatever they are.

[Altera_Forum]

When I said dummy samples I mean you just assert valid and it doesn't matter what value goes on the input at that point. It will produce "fake" results, but it doesn't matter as you will only be selecting the results from the channels you care about.

[Altera_Forum]

I didn't describe the problem, my fault. 

 I have 11 fir filters connected in series, each with decimation factor = 2, clock frequence = 120 kHz,same coefficients and different input sample rates (because of the decimation): 1. 120 kHz 2. 60 kHz 3. 30 kHz 4. 15 kHz 5. 7500 Hz 6. 3750 Hz 7. 1875 Hz 8. 937,5 Hz 9. 468,75 Hz 10. 234,375 Hz 11. 117,1875 kHz It's working, but can't fit in our FPGA, even in case of increasing clock frequence.  Thats why I want to do it with one filter and 11 channels. So, I want to use this channels with different frequences.  I hope I explained the problem clear. What do you think about it?

[Altera_Forum]

--- Quote Start ---  I didn't describe the problem, my fault.  I have 11 fir filters connected in series, each with decimation factor = 2, clock frequence = 120 kHz,same coefficients and different input sample rates (because of the decimation): 1. 120 kHz 2. 60 kHz 3. 30 kHz 4. 15 kHz 5. 7500 Hz 6. 3750 Hz 7. 1875 Hz 8. 937,5 Hz 9. 468,75 Hz 10. 234,375 Hz 11. 117,1875 kHz It's working, but can't fit in our FPGA, even in case of increasing clock frequence.  Thats why I want to do it with one filter and 11 channels. So, I want to use this channels with different frequences.  I hope I explained the problem clear. What do you think about it?  --- Quote End ---    if your sampling rate is halved each time then you can't use multichannel as it expects one sample rate.  You can decimate in a cascade but filters need not be identical as that is a waste of resource.  you can reduce the burden on cutoff point as you go down the cascade. Alternatively you can decimate in one filter and that will also reduce resource due to decimation effect internally.

[Altera_Forum]

At these rates, unless you have a huge number of taps, you might just be able to do this in software with a fast Nios (with a hardware multiplier). By interleaving the FIR sequences, the top bandwidth uses 1 in 2 sequences, the next 1 in 4 and so on, you can fit in an infinite number of decimations - each decimation of course needs its own set of sample memory registers. However, you need them even if it is all done in hardware.  

 As Kaz points out, if you do use the FIR blocks, only the last in the chain needs all those taps.