FPGA 2 SDRAM interface

[Altera_Forum]

I’m working with the Cyclone V SoC dev kit and I’m trying to get maximum throughput of data from the FPGA to the HPS SDRAM. I’ve been trying to get the fpga2sdram interface working, but I’ve been unsuccessful. I've generated the preloader binary, u-boot.img, and updated the device tree. I’m programming the FPGA and running the “bridge_enable_handoff” in U-boot. However, when Linux starts booting it always hangs. I've made sure that the FPGA side is not initiating any transactions during that time (i.e. no write/read requests). The waitrequest signal does stay low on the f2hsdram interface, but it's like enabling that bridge doesn't allow Linux access to the memory.  

 I've been trying to get it working using my own Avalon MM logic which is working fine with a frame buffer using the FPGA DDR3 memory, but I'm worried that I might have to instantiate a DMA controller in Qsys for this like I've seen in other posts. Is that necessary? Are there some security bits that need setting or something? If you could point me to any example that would be extremely helpful. Thanks for any reply.

[Altera_Forum]

Just figured out my problem and I thought I'd reply to this to help out people like me out there... 

 It was the "portdefault" bits in the "protportdefault" SDRAM controller register. They were all set to "1" and not allowing access to the port! I thought this would have been accounted for in the mountain of u-boot code.   I added this to the u-boot.scr after "run bridge_enable_handoff":  mw 0xffc2508c 0;