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Altera_Forum
Honored Contributor I
924 Views

FPGA Counter Catch Eight game(error 10476, error 10558)

hi, 

im new to VHDL coding as im still learning the basics, i need to design a counter catch eight game and i have done the code but it shows and error and i am not able to solve it. it will be very helpful if anyone can help me wit this codes 

 

 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12644&stc=1  

the error is shown in the picture.....
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5 Replies
Altera_Forum
Honored Contributor I
90 Views

The 3rd port of your 'Counter' module is an 'unsigned' signal type and you're trying to connect 'clock_output', a 'std_logic' signal to it. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
90 Views

 

--- Quote Start ---  

The 3rd port of your 'Counter' module is an 'unsigned' signal type and you're trying to connect 'clock_output', a 'std_logic' signal to it. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

 

hi mr alex,  

if i send u my full code will be able to able to fix it for me because as i know i already the sign these signals in the counter. Are u able to help pls?? if can pls drop me ur email, i'll send u my full code in notepad :)
Altera_Forum
Honored Contributor I
90 Views

You can attach any code to this post - I suggest the code for your 'Counter' module. 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
90 Views

 

--- Quote Start ---  

You can attach any code to this post - I suggest the code for your 'Counter' module. 

Cheers, 

Alex 

--- Quote End ---  

 

 

 

---counter 

library IEEE; 

use IEEE.std_logic_1164.all; 

use IEEE.std_logic_arith.all; 

 

entity Counter is 

port( 

CLK: in std_logic; 

RST: in std_logic; 

Digit1_Output: out unsigned(3 downto 0) 

); 

end Counter; 

 

architecture Counter_arch of Counter is 

signal Digit1: unsigned(3 downto 0); 

 

begin 

 

process(CLK,RST) 

begin 

if RST = '0' then 

Digit1 <= (others=>'0'); 

elsif rising_edge(CLK)then 

if Digit1 < 9 then 

Digit1 <= Digit1 + 1; 

else 

Digit1 <= (others=>'0'); 

end if; 

end if; 

end process; 

 

Digit1_Output <= Digit1; 

 

end Counter_arch;
Altera_Forum
Honored Contributor I
90 Views

So, 'Digit1_Output' is a 4-bit value. Which bit of that are you trying to connect your std_logic 'clock_output' to? 

 

I suggest you change 

Digit1_Output: out unsigned(3 downto 0) 

to 

Digit1_Output: out std_logic_vector(3 downto 0) 

At the top level connect a new 4-bit std_logic_vector signal in place of 'clock_output' and then connect 'clock_output' to whichever bit of 'Digit1_Output' you need. 

 

Cheers, 

Alex
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