FPGA GPIO voltage falling

[Altera_Forum]

Hi, 

 as part of my final project for elecronic engineering, Ii have designed a 8051 based SoC with SPI master/slave interface.  The problem I am facing is as followos: When I transmit SPI data to the SoC SPI slave interface, the voltage level falls to ~1.6v instead of 3.3.  the SPI clock behaves fine. only data and chip select fall. i noticed, the voltage fall started only afetr first transmition.   I added to the GPIOs, weak pull-up's but with no help.  please your advice...  BTW, i am using cycloneII on DE2 board with quartus 13.0

[Altera_Forum]

This sounds like you have the signal directions wrong. 

 SPI devices often have pins with names like; selN, sck, sdi, and sdo. The port names "serial data in" and "serial data out" are ambiguous, since those names at the slave do not correspond to those same directions at the SPI master, so the industry has adopted the namng convention miso "master in/slave out" and mosi "master out/slave in".  I'd recommend checking that your FPGA output is connected to the SPI slave *input*.   Since you are seeing the voltage drop to ~half, I suspect you have the FPGA output driving the SPI slave output.  Cheers, Dave

[Altera_Forum]

Hi, thanks for the answer. 

 I did some "debug", and found out, the problem was caused by my BIDIR ports of the SPI slave (my design enables QSPI). once i defined the port as input only, the voltage was O.k.  after some more debug, i realized, that for some strange reason, the FSM read flag was raised => the inputs were turned over to output (thus explaining why the voltage fell after the first byte...).  this is very wierd since i sent a"write" command, and according to my test block, the command was accepted correctly by the slave.  do you have any idea how could a signal go high even though on simulation it didn't?

[Altera_Forum]

--- Quote Start ---   I did some "debug", and found out, the problem was caused by my BIDIR ports of the SPI slave (my design enables QSPI). once i defined the port as input only, the voltage was O.k.   --- Quote End ---   Great! Its unlikely you damaged anything, since both drivers were "fighting" with about the same strength (no-one won).    --- Quote Start ---   after some more debug, i realized, that for some strange reason, the FSM read flag was raised => the inputs were turned over to output (thus explaining why the voltage fell after the first byte...).  this is very wierd since i sent a"write" command, and according to my test block, the command was accepted correctly by the slave.  do you have any idea how could a signal go high even though on simulation it didn't?  --- Quote End ---    That sounds like a synchronization issue, eg., you're looking at signals from outside the FPGA that are not synchronous to your FSM clock. Check you have included synchronization logic where it is needed, and that you have correct timing constraints in your design.  This thread has a TimeQuest example for QSPI flash  http://www.alteraforum.com/forum/showthread.php?t=41009  Cheers, Dave