FPGA Impementation Digital Clock

Altera_Forum · ‎04-19-2010

Hi,

I need to design digital clock allow global reset and allow user to adjust min and hour.I have done the min and second from 0 to 59 but i having a problem to design a counter 0 to 23.

This is the VHDL that i write but i dunno why my counter 0 to 23 1 times only...after 1 times run finish it will straight away jump to 11 until 23....

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

entity counter0_to_23 is

port( CLK,Reset,E: in std_logic;

Q_MSB : buffer std_logic_vector (3 downto 0);

Q_LSB : buffer std_logic_vector (3 downto 0));

end counter0_to_23;

architecture structural of counter0_to_23 is

component or_4 is

port( in1,in2,in3,in4: in std_logic;

out1 : out std_logic);

end component;

component not_1 is

port( in1: in std_logic;

out1: out std_logic);

end component;

component or_2 is

port ( in1,in2: in std_logic;

out1 : out std_logic);

end component;

component and_8 is

port (in1,in2,in3,in4,in5,in6,in7,in8: IN STD_LOGIC;

out1 : OUT STD_LOGIC);

end component;

component decade_counter is

port (CLK,Reset,E :in std_logic;

Q :out std_logic_vector(3 downto 0));

end component;

signal or_out : std_logic_vector(1 downto 0);

signal not_out: std_logic_vector(6 downto 0);

signal and_out: std_logic;

begin

U1: decade_counter port map (CLK,or_out(0),E,Q_LSB(3 downto 0));

U2: not_1 port map (Q_LSB(0),not_out(1));

U3: not_1 port map (Q_LSB(1),not_out(2));

U4: not_1 port map (Q_LSB(3),not_out(3));

U5: not_1 port map (Q_MSB(0),not_out(4));

U6: not_1 port map (Q_MSB(2),not_out(5));

U7: not_1 port map (Q_MSB(3),not_out(6));

U8: and_8 port map (not_out(1),not_out(2),not_out(3),not_out(4),not_out(5),not_out(6),Q_LSB(2),Q_MSB(1),and_out);

U9: or_2 port map (Reset,and_out,or_out(0));

U10: or_4 port map (Q_LSB(0),Q_LSB(1),Q_LSB(2),Q_LSB(3),or_out(1));

U11: not_1 port map (or_out(1),not_out(0));

U12: decade_counter port map (not_out(0),or_out(0),E,Q_MSB(3 downto 0));

end structural;

Altera_Forum · ‎04-19-2010

What you have done isnt really VHDL - you've just created a netlist of components. You can do much better looking stuff in vhdl like this:


signal minute : integer range 0 to 59;
signal hour : integer range 0 to 23;
process(clk)
begin
  if rising_edge(clk) then
    if progress_minute then
      if minute = 59 then
        minute <= 0;
 
        if hour = 23 then
          hour <= 0;
        else
          hour <= hour + 1;
        end if;
      else
        minute <= minute + 1;
      end if;
    end if;
  end if;
end process;

Altera_Forum · ‎04-20-2010

thk for your answer...

if using the structural how should i write it....

Altera_Forum · ‎04-20-2010

--- Quote Start ---

What you have done isnt really VHDL - you've just created a netlist of components. You can do much better looking stuff in vhdl like this:


signal minute : integer range 0 to 59;
signal hour : integer range 0 to 23;
 
process(clk)
begin
  if rising_edge(clk) then
    if progress_minute then
      if minute = 59 then
        minute <= 0;
 
        if hour = 23 then
          hour <= 0;
        else
          hour <= hour + 1;
        end if;
      else
        minute <= minute + 1;
      end if;
    end if;
  end if;
end process;

--- Quote End ---

Thank for your reply...

If i want to design by using structural how should i write???