Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

FPGA Mechanical Pressure Limit

Altera_Forum
Honored Contributor II
‎03-05-2010 04:29 PM
3,855 Views

We are using the FPGA Stratix IV (EP4SE530H35C3NES) using an adhesive backed heat sink. 

 

The heat sink vendor recommends 10 psi of pressure for obtaining a good bond but that translates into 28 lbs of force on the device. 

 

What is the maximum or recommend force/pressure that can be applied to this device? 

 

Thanks, 

Joe
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎03-08-2010 04:10 PM
2,962 Views

Not a guarantee... I'm not Altera. But it's highly unlikely that the device would break under that load, evenly distributed. Assuming it is already on a board, you simply need to have the whole board resting on some compliant, yet firm surface (rubber pad, electrostatically protected). Your worst case scenario would be pressing on the middle of a board that is supported elsewhere (i.e. the corners, edges). The first thing to fail would be the solder itself, or the delamination of the surface copper layers, and it could occur under the FPGA or any other chip, due to the board flexure.

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.