FPGA design that overloads the FPGA and varing it's power consumption

[Gyud0]

Hey,

I'm looking for a FPGA design that overloads the FPGA and alter it's power consumption by a demanding (it can be configured by a generic ports).

Do you know something about it?

Thank you

[FvM]

Hi,
not clear what you mean with overload? You can generate a test design with maximal core current consumption by clocking many ("all") logic cells at highest supported frequency and make it switch at high rate. E.g. feed at huge register chain with 01 sequence.

Regards,
Frank

[lixy]

Hi,

As FvM asked, I also wonder what "Overload" meant. Also, what is the FPGA device you are using?

I did know that some device supports Dynamic Reconfiguration" for Transceivers, which allows you to dynamically reconfigure different portions of the transceivers without powering down any part of the device. But I am not sure if this is what you are referring to.

Thanks & Regards,

XY

[Gyud0]

Hey again,

I mean that I need a design (or a guidance) that consumes a lot of ALMs and it makes the FPGA to consume more power.

And in the next level, I would like to control how many ALMs this design requires. 

[_AK6DN_]

Make a long shift register with multiple taps.

Like really long, 100K to 250K bits, whatever you do to get to 75% or more utilization on your target device.

Then feed an alternating 0/1 pattern into it, causing 100% activity on those logic paths.

And maybe provide several intermediate points where you can force in a 0 or 1 to disable trailing cells, to allow tailoring your power consumption.

And use a variable frequency master clock input as well to allow varying overall power consumption.

[lixy]

Hi there,

1, I need a design (or a guidance) that consumes a lot of ALMs and it makes the FPGA to consume more power.

We do not have an exact design which is dedicated to consume as much as FPGA ALM resource. I can only suggest some general and simple notes. You can check in Quartus Compilation Report and check how many ALMs are used.

For RTL design and Logic: 1) Use more parallel logics, such as high-width signal calculation, repeating certain logic modules. 2) Use deeper pipeline structure.

For Timing: 1) User higher clock frequency. 2) Set constraints more strictly which would leads to higher resource usage.

2, And in the next level, I would like to control how many ALMs this design requires. 

If you would like to know how to reduce the ALM resources used in your design, you can refer to Intel® Quartus® Prime Pro Edition User Guide: Design Optimization and see if it meets your need.(https://www.intel.com/content/www/us/en/docs/programmable/683641/23-2/faq.html)

If you meant that you wants to adjust how many ALMs are used when the FPGA is running, it is actually not applicable. The resource used in your design is fixed after Fitting (placing and routing). If you wants to change the ALM resource used in FPGA, you have to do reconfiguration (Simply reconfiguring a new design, Partial Reconfiguration, or Dynamic Reconfiguration.)

Thanks & Regards,

Xiaoyan