FPGA giving out partial answer

[Navaneeth]

Hi,

We expect 9216 bytes of data as output from the FPGA, but we only get 1536 bytes of data. We have thoroughly verified our logic design using the ASE Simulator wherein we are correctly obtaining the required 9216 bytes of data as output without facing any issues.

Timing constraints are also met while synthesizing our design!

Please can you help by mentioning any guidance / how ASE and FPGA are different / what further factors should we consider which are causing points of difference b/w ASE and FPGA runs?

Thank you, anticipate reply/replies at the earliest.

[Kenny_Tan]

Hi,

Thanks for using Intel community forum,

Kindly expect some delay in the reply due to holiday.

Thanks,

Kenny

[Michael19]

Hi,

without any information about your design except the two numbers, its a bit difficult to say anything.

Maybe the answer is 42 ?

But nevertheless, there is a hint here: 1536 Bytes is the maximum length of an standard ethernet frame. 

If your data is somehow passing through a MAC somewere in your test setup, it will be truncated there.

But this behaviour usually can be switched off. Ethernet also defines so called Jumbo-Frames, which may be much larger.

Usage of these, i think, is not enabled per default.

Check your  MAC -IPs. Presumably somewhere there is a parameter enforcing a maximum frame size of 1536.

Switch it off to allow long frames.

Might be called  "enforce maximum frame size" or something like this. 

[SyafieqS]

Hi Navaneeth,

Can you verify what is suggested by Michael?

If it is still persist, can you tap signals and see what path(s) is causing the issue?

[SyafieqS]

Hi Navaneeth,

May I know if there is any update?

[SyafieqS]

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

[Navaneeth]

Hi,

Really sorry for not updating here. We have put a pause on the project as we are involved in other work and also, we recently noticed that one of the components that we treated as a black box in our design is not functionally working as expected in ASE itself and also on FPGA ( both these conclusions we reached by testing out the black box alone without adding our surrounding logic ).

Thanks for the help
And sorry for the trouble
We will debug the issue inside the black box as our next step