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FPGA image booting and NioS system booting

osi-hw
Novice
537 Views

Hi, 

So my system has a cyclone V with a nios processor.

This FPGA is configured using CPLD MAX 10.

The configuration mode for cyclone V is passive serial ( PS ). 

The nios and FPGA can boot when pointing both reset vector and exception vector on the OCRAM. But now the Nios application image is bigger than the maximum OCRAM size and the solution is to run the application on DDR. 

How can I achieve that ?

PS: The CPLD is connected to a parallel flash , and the cyclone V is also connected to the parallel flash but the configuration mode is passive serial not passive parallel 

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1 Solution
ShengN_Intel
Employee
506 Views

Hi,

 

Can try Nios II Processor Booting from CFI Flash if using Cyclone V check this https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-from-cfi-flash.html

 

Then probably can set the configuration scheme and mode to passive serial as The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP) scheme. Check this https://www.intel.com/content/www/us/en/docs/programmable/683698/21-1-19-1-0/supported-schemes-and-features.html

ShengN_Intel_0-1656399580687.png

Pointing both reset vector and exception vector to Parallel Flash and External RAM (DDR) respectively.

 

Here are some references may be helpful to you:

https://community.intel.com/t5/FPGA-Wiki/Nios-II-Booting-From-CFI/ta-p/735490

https://malt.zendesk.com/hc/ja/articles/900006257703-Nios-II-Boot-Option-CFI-Flash-

 

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

View solution in original post

1 Reply
ShengN_Intel
Employee
507 Views

Hi,

 

Can try Nios II Processor Booting from CFI Flash if using Cyclone V check this https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-from-cfi-flash.html

 

Then probably can set the configuration scheme and mode to passive serial as The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP) scheme. Check this https://www.intel.com/content/www/us/en/docs/programmable/683698/21-1-19-1-0/supported-schemes-and-features.html

ShengN_Intel_0-1656399580687.png

Pointing both reset vector and exception vector to Parallel Flash and External RAM (DDR) respectively.

 

Here are some references may be helpful to you:

https://community.intel.com/t5/FPGA-Wiki/Nios-II-Booting-From-CFI/ta-p/735490

https://malt.zendesk.com/hc/ja/articles/900006257703-Nios-II-Boot-Option-CFI-Flash-

 

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.

 

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