FPGA is not responding to code

[Altera_Forum]

Hello, 

 I have downloaded vhdl code in cyclone III fpga. But fpga is not responding after downloading. I have two vhdl codes. When I download first vhdl code, fpga works fine. But when I download second code (first code with some modification), fpga doesn't respond. Can any one tell me what can be the possible root cause of this?  the total resources that second code is utilizing are less than first one...

[Altera_Forum]

It sounds like your 'modification' to the second code breaks it functionally. If it's using up fewer resources than you expect then something's wrong. I suspect you've made a small error in your code that results in a portion of functionality being removed. Hence, it's not as big as you're expecting nor does it do as you expect. 

 Do both design simulate as you'd expect? I suspect not...  Cheers, Alex

[Altera_Forum]

I think it is recommended to perform a functional simulation ie with Modelsim before you start the hardware testing. This would ease the debugging since it is still at functional level. At hardware level, there are more factors to consider during debugging.

[Altera_Forum]

No error after running full compilation?

[Altera_Forum]

--- Quote Start ---  No error after running full compilation?  --- Quote End ---    No error at all

[Altera_Forum]

Put some breakpoints in your code, run the simulation and see which line caused the problem.

[Altera_Forum]

I could suggest you add in a state monitor eg. using register to monitor the vhld code simulation. At hardward side pls use singaltap to monitor state transition.

[Altera_Forum]

What is all this talk of breakpoints, signaltap etc? 

Surely the OP had a good testbench - did the second set of code pass through the same testbench as the first code?  If you want some help with a problem - you need to post the code so we can actually help.

[Altera_Forum]

Hello, please describe what is the observation is details. How you define its working or not working. most of the time, the problem come from the design codes, and not the FPGA.

[Altera_Forum]

Yes, please post a code at least we can help to look at it.