FPGA process LVDS serial differential ADC issue

[MinzhiWang]

Hi there, 

We are designing board's schematic. The board will use Cyclone 10 GX FPGA devices. Several AD9633 devices output LVDS serail differential pairs will be connected to this FPGA.

We know that the LVDS data pairs will connect to FPGA's LVDS receiver pairs. Our question is how to process ADC's output syncronized clock pair(DCO+/-)? Can we connect this clock pair to normal LVDS IO pair or to didcated clock input pair? The DCO+/- pair should be used as LVDS logic syncroniazed clock.

BTW, can the differental pairs be used as LVDS pair in bank2L? Which are named as "DIFFIO2L_*P/N".

[FvM]

Hi,

first step is do decide about the synchronization method. It determines which ADC signals need to be connected and if they have to be routed to dedicated clock inputs.

If DCO is used as a clock in your design, it has to be routed to a dedicated clock input. If you want to use 10CX SERDES, only dedicated RX channels can be used, e.g. not bank 2L.

[AqidAyman_Intel]

Hello,

I think you will need to use dedicated clock input pins for DCO as if the DCO is used for the external clock input for your design. You can refer to the link below for reference:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/clocking-differential-receivers.html

As for Bank 2L, it is a 3V I/O bank which supports differential SSTL, HSTL, and HSUL I/O standards up to 3 V. For the LVDS, Intel Cyclone 10 GX supports it on all LVDS I/O banks. Refer to below links for more information:

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/i-o-and-differential-i-o-buffers-in-devices.html

https://www.intel.com/content/www/us/en/docs/programmable/683775/current/i-o-banks-groups-in-devices.html

Regards,

Aqid