FPGA replace CPLD

[Altera_Forum]

I have a hdl program with several array such as [31:0] , [12:0] and [16:0] , only FPGA can holds such a large memory , one problem I faced is no NIOS II CPU is used and wish to remember the program after power off like CPLD , how can I flash the FPGA just like this action ??

[Altera_Forum]

you need an external flash memory, such an an EPCS, and connect if to the FPGA. Then store your design in the flash and the FPGA will be configured at power on.

[Altera_Forum]

Is it doing so in quartus (program device) part ??

[Altera_Forum]

You can program a serial flash with a USB blaster and the Quartus programmer. You can either put a contact on your board for the USB blaster to connect it directly to the flash, or on some FPGAs use the Serial Flash Loader design that will let the Quartus programmer access the flash through JTAG. 

Which FPGA are you using?

[Altera_Forum]

MY FPGA is EP2C8Q208

[Altera_Forum]

The serial flash loader can only be used on Cyclones III or later, so with a Cyclone II you will have to put a connector to configure the flash memory, in addition to the JTAG connector. Have a look at figure 13-7 in this document (http://www.altera.com/literature/hb/cyc2/cyc2_cii51013.pdf). (and you should read all this document, it has interesting information about configuration).