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FPGA schematic design - JTAG and EPCQA

NShan12
New Contributor I
289 Views

Hello,

 

I am designing a custom board with Cyclone 10 LP FPGA - 10CL080YU484A7G. I have the following questions:

a) Should the VREFB pins be connected to Ground or VCCIO? I use same IO voltage of 1.2V for all banks.

NShan12_0-1626857235378.png

 

b) Cyclone 10 Handbook mentions that pull up resistors of FPGA device to be connected to VCC of the bank in which the JTAG pins reside. I do not understand this point. Could you please elaborate? Is this a setting in Quartus Prime? Or any connections to be made in the board schematics?

Is this anything related to RUP and RDN pins of FPGA? I am using some of the RUP and RDN as user IO.

 

NShan12_1-1626857352198.png

 

I am using the SFL core for in system configuration using JTAG. Supply voltage to JTAG connector is VCCA (2.5 V in my case). If JTAG signals are at VCCA (2.5V logic) and VCCIO of FPGA is 3.3V, will this work?

NShan12_2-1626858273455.png

 

Thank you!

 

 

 

 

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3 Replies
AminT_Intel
Employee
249 Views

Hello,

 

Please refer to these links for your reference design: 

1. Cyclone 10 LP GPIO User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.p...

2. Cyclone 10 LP Device Datasheet: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51002.p...

3. Cyclone 10 LP Pin Connection Guideline: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01021.pdf

 

The answer is yes to the second question. You can use Pin Planner to program this setting. 

 

Please refer to I/O Standard table from page 78 and see your setting meet the guideline.

 

Thank you.

NShan12
New Contributor I
225 Views

Hello,

Thank you for your answer. I have referred the documents.

It is still not clear for me: "pull up resistors of FPGA device to be connected to VCC of the bank in which the JTAG pins reside"

NShan12_1-1627292772613.png

The above diagram shows the JTAG connector pins are connected to VCCA, which is 2.5 V and FPGA pull ups connected to VCC of the bank i.e VCCIO = 3.3V. Is this not a mismatch?

 

 

 

 

AminT_Intel
Employee
184 Views

Hello,

 

That is the guideline where you configure Intel Cyclone 10 LP Device where you need to connect the pull up resistor of the device to Vcc in which the pin resides.

 

You can configure pins using Pin Planner. 

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