FPGA specific timing requirement

[Altera_Forum]

I need to output a pulse signal from the FPGA that is very time sensitive. I would like to have control of the period by a resolution of 2 ns. This would require a 500 MHz output clock. Briefly looking at the cyclone III, it seems that this is not possible; however, it says it can reach 400 MHz, which might be good enough. 

 I'm wondering if there is a way to reach my goal of a 2 ns resolution using a cyclone III and if not is there another board that can achieve this? Also, if need be can I clock the cyclone III at 400 MHz to be used as the timer for the period? I have seen a lot of posts regarding that even though the specs say it can be clocked at certain speeds, the circuit might not work correctly at those speeds. Any help will be greatly appreciated.

[Altera_Forum]

Hi,  

 Cyclone III supports DDR (Double Data Rate) outputs, so you can control a pulse's width in 2ns increments using a 250 MHz clock.  The maximum frequency that the FPGA will actually work correctly will depend on many things: design, I/O characteristics, etc.  The only way to know for sure is to implement a design and validate it using STA (Static Timming Analysis) and gate level simulation.  Important question: what kind of signals are you using? LVCMOS? LVDS?

[Altera_Forum]

As I said it is just a square wave that is high and low. I want to control the period of this pulse wave to control the period of the device it turns on and off. It would just be driving one output pin high and low but to the accuracy of 2 ns.  

 Does the signal type matter in this case? I thought those signal types were mainly for data transfers not something that would be needed for an output as simple as this. This is my first time trying to combine an FPGA with another device, so forgive my ignorance.  EDIT: If you're referring to the input signals then yes they will be LVDS.

[Altera_Forum]

All digital signals are just "square" waves that are high and low... :) 

 You must understand that you are getting close to the limits of what FPGAs can do and weather what you need can be done or not, depends on the fine details.  Signal type may matter, both inputs and outputs. There are physical and hardware limitations and those limitations are different for different types of signal. ie, CMOS signals are larger and cause more noise than LVDS. Thus, LVDS signals can be used at much higher frequencies than CMOS.  Anyway, I'm still trying to grap what you need to do. Do you need to produce a square wave (that is, a clock like signal) and control the period with a 2ns resolution? Or do you need to produce pulses of "1" where the pulse length is controlled to a 2ns resolution?

[Altera_Forum]

I basically have a max period of 2us. In this period I need to pulse one signal and then turn it off and pulse another signal and turn it off. The next period of this firing will then change by a measurement with a resolution of 2ns. These signals are like a clock you could say as they enable the device they're pulsing to turn on and off. 

 Bascially, I need to have very precise control over the frequency i'm pulsing because I only have a very small bandwith that i'm working with and the slope is very steep over this bandwith so that a few hundred Hz difference can produce a big difference in my output. With 2ns resolution i'm looking at only a resolution of 320 Hz.   EDIT: For clarity

[Altera_Forum]

If I understood your needs correctly, it can be done. 

 Basically, what you need to do is use a 250 MHz (4ns) clock and DDR outputs. With DDR outputs, you can set a different value for each half of the clock cycle, thus you get your 2ns resolution. You can even go higher than that.

[Altera_Forum]

Essentialy I would just be using the rising and falling edges of the clock instead of just the rising?

[Altera_Forum]

Essentially, if I had a worse case scenario and my input wave was 400KHz, which is 2.5 us period. If I wanted to produce an output of a pulse from two different signals at 2.499 us or basically turn one pulse on for x of time then off and then turn the other on for x and then off and have this period be 2.449 us. Is that doable? Also, could I do even better, lets say 0.5 ns?  

 My thoughts were to use a counter. I read some posts where people mentioned using 4 different phase changed clocks at 250MHzto achieve a 1GHz rate. Is that something that will work for me?

[Altera_Forum]

Yes, using both edges of the clock. 

 By better, I meant a bit better than 2 ns but way above 1 ns. In the end, your resolutions is going to be limited not just by FPGAs internals but also by the signal's rise/fall time, noise, etc.  If the on time or the off time is very short (say, 2 ns), you might run into minimum pulse width issues, if you're using, say, 3.3 LVCMOS signals.  Board design will be important.  I'm not seeing how to combine 4 clocks with different phases to produce a better resolution. It may be possible, but I don't see how.

[Altera_Forum]

Thanks for the information. That should be good enough for what I'm doing.