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FPGA to SDRAM port access problem

Altera_Forum
Honored Contributor II
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Hello, 

 

I have a data file that is read by the HPS... I'm assuming the data block is stored in the SDRAM. This is the C code I used: 

 

volatile char *address_pointer = (char*)malloc(bufflength1); //bufflength1 is length of datablock. Approx< 65k. 

n=fread(address_pointer,bufflength1,1,f); 

 

When I debug, address_pointer = 0x043CB178 

 

This is the same address I tell the master to start reading the data from... 

I want the FPGA to read this data block and process it (and eventually return results to the HPS). 

I implemented FPGA-SDRAM Avalon-MM port in the HPS. There is a read master (fft_memory in Fig 1) that connects to the fpga-sdram slave. 

The master however fails to read data as the master_wait_request is always high.  

 

Is there something else I need to set/reset before trying to use the SDRAM from the FPGA end?? 

 

or is there any other concept like base addresses/ offset that I need to take into consideration? 

 

Any help is appreciated!!
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Altera_Forum
Honored Contributor II
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Hello surabhisgp, 

 

i have a similar problem accessing the HPS sdram from NIOS II (http://www.alteraforum.com/forum/showthread.php?t=50754). 

 

Did you find a solution? 

 

Thanks in advance, Patrick
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Altera_Forum
Honored Contributor II
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Pls both build up a new Preloader (SPL) and then free the bridges in uboot with the correct fpga2sdram_handoff

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Altera_Forum
Honored Contributor II
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Hello, 

 

i will post my results in http://www.alteraforum.com/forum/showthread.php?t=50754 

 

Thanks, 

 

Patrick
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Altera_Forum
Honored Contributor II
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Hello Patrick, 

 

No I didn't find a way around it. 

Like others suggested, I did also build the preloader using bsp editor but not too sure what 'free the bridges' means. 

Anyway, I abandoned the board after a while and went back to using a cyclone 4. 

 

Surabhi
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