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Altera_Forum
Honored Contributor I
2,210 Views

FPGA to SFP

I have designed Cyclone V based FPGA board. 

 

But i have connected with Normal IO instead of Transceiver IO. 

 

I need to clarify, whether this will work or not. 

 

I have attached schematic design.
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10 Replies
Altera_Forum
Honored Contributor I
310 Views

This will depend on how fast you're hoping to operate the SFP module. At 1Gbps? Then no - it's not likely to work. If the SFP will run @ 400Mbps, and that's acceptable to you, then yes - you may be able to get it working. 

 

Refer to Table 33: 'High-Speed I/O Specifications for Cyclone V Devices' - in the "cyclone v device datasheet (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_51002.pdf)" for the max differential data rates you can expect for 'normal' I/O. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
310 Views

Hi Alex, 

 

Thanks for your reply. 

 

I would like to know, is there any AC coupling needed between FPGA and SFP. 

 

Because, while loop back testing SFP module I am always getting 1 output. 

 

May I know the difference between Normal IO vs Transceiver IO.
Altera_Forum
Honored Contributor I
310 Views

SFP transceivers are AC coupled (already inside the module). You get only correct output with DC balanced signal, e.g. 8b/10b encoded. If you use LVDS I/O standard with Cyclone 5, add external DC bias for RX. 

 

There are 622 MBPS SFP modules that should work with Cyclone V standard SERDES. 1 GBPS modules are not specified for lower data rates, I presume they'll work at 400 - 600 MBPS as well. 

 

 

--- Quote Start ---  

May I know the difference between Normal IO vs Transceiver IO. 

--- Quote End ---  

 

Gigabit transceivers of GX/GT devices have fast receiver hardware for 614 MBPS to 3.1/6.1 GBPS.
Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

I have designed for SFP loopback test. But I didnt receive any output. 

--- Quote End ---  

 

How did you setup the test? What's the IO configuration?
Altera_Forum
Honored Contributor I
310 Views

What happens if we connect the SFP differential transmitter and receiver pin with FPGA differential IO pin instead of Transceiver IO in Cyclone V FPGA.? 

 

What are the IP needed to communicate FPGA with SFP.? 

 

Please clarify.?
Altera_Forum
Honored Contributor I
310 Views

Then it's possible to achieve the I/O speeds specified in the 'High-Speed I/O Specifications for Cyclone V Devices' section of the datasheet. 

 

What IP? This depends on what you want to do - you don't necessarily need any. 

 

Altera offer a 'serial gigabit media independent interface (https://www.altera.com/solutions/technology/transceiver/protocols/pro-sgmii.html)', but you might struggle to get that working given how you've connected up your SFP. 

 

Cheers, 

Alex
Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

Then it's possible to achieve the I/O speeds specified in the 'High-Speed I/O Specifications for Cyclone V Devices' section of the datasheet. 

 

What IP? This depends on what you want to do - you don't necessarily need any. 

 

Altera offer a 'serial gigabit media independent interface (https://www.altera.com/solutions/technology/transceiver/protocols/pro-sgmii.html)', but you might struggle to get that working given how you've connected up your SFP. 

 

Cheers, 

Alex 

--- Quote End ---  

 

 

 

I tried to implement SFP without IP. 

 

But i am struck up with output.
Altera_Forum
Honored Contributor I
310 Views

SFP modules are AC coupled (inline capacitors within the module) by design. Driving the SFP using two single ended outputs in a pseudo-differential mode can be made to work (especially at lower signal bandwidths like 100Mb ethernet or 155Mb OC3). Once you get to 622Mb OC12 or higher using this mode is not likely to work well. 

 

Receiving however is a different matter. Since the signals are AC coupled, at the SFP pins you will see single ended signal swings around 0V DC (like -1V to +1V). These levels are not within the valid input range for a single ended receiver, which will be 0V to some VCCIO like 3.3V/2.5V/1.8V. You must terminate the signals in the correct line impedance (ie, 40 to 80 ohms, depending on layout) to maintain signal quality, AND add a DC offset to move the signal into the switching range of the receiver. 

 

Typical boards that interface to SFP modules have resistive termination circuits that perform the termination/restore to (usually) 100ohm differential and a Vt that depends on the receiver, typically this is VCCIO-1.2V or so. 

 

So I think you need to rethink your board design. Just connecting an SFP module to single ended I/O on the FPGA with no external signal conditioning circuit will not work.
Altera_Forum
Honored Contributor I
310 Views

 

--- Quote Start ---  

SFP modules are AC coupled (inline capacitors within the module) by design. Driving the SFP using two single ended outputs in a pseudo-differential mode can be made to work (especially at lower signal bandwidths like 100Mb ethernet or 155Mb OC3). Once you get to 622Mb OC12 or higher using this mode is not likely to work well. 

 

Receiving however is a different matter. Since the signals are AC coupled, at the SFP pins you will see single ended signal swings around 0V DC (like -1V to +1V). These levels are not within the valid input range for a single ended receiver, which will be 0V to some VCCIO like 3.3V/2.5V/1.8V. You must terminate the signals in the correct line impedance (ie, 40 to 80 ohms, depending on layout) to maintain signal quality, AND add a DC offset to move the signal into the switching range of the receiver. 

 

Typical boards that interface to SFP modules have resistive termination circuits that perform the termination/restore to (usually) 100ohm differential and a Vt that depends on the receiver, typically this is VCCIO-1.2V or so. 

 

So I think you need to rethink your board design. Just connecting an SFP module to single ended I/O on the FPGA with no external signal conditioning circuit will not work. 

--- Quote End ---  

 

 

 

Hi, 

 

Thanks for your reply. 

 

As per your guideline, i have designed breakout board for LVDS driver and signal conditioning. 

 

Here i need clarification in the design. This LVDS driver will be 100ohm impedance. I would like to know, whether both FPGA differential IO pin and SFP transceiver pins are 100ohm impedance or different impedance. 

 

I have attached schematic of the breakout. 

 

Please verify, whether it is ok or not.?
Altera_Forum
Honored Contributor I
310 Views

Have you read the TI datasheet for this device? Specifically section 11.2.8 describes how to do AC coupled signal reception (which will be what you get from the SFP module output). Basically you need 50ohm pullups on both P/N to Vbb. Read the datasheet for all the details. 

 

The TX input into the SFP will be just direct wires, as the SFP module is internally AC coupled and has 100ohm differential termination across P/N. 

 

Note the 100ohm differential / 50ohm single-ended signal termination and routing means you adhere to those rules when designing the PCB trace layout, and implement the appropriate trace widths and spacing on your PCB to give you those trace impedances.