FSM design/reset

[Altera_Forum]

Hi! I'm currently implementing some control logic using an FSM on a Stratix II chip. I'm having issues writing a "clean" FSM design, as I don't have an external reset signal available. My questions are therefore: 

1. Does the Stratix II have some kind of internal reset signal available after powerup (documentation is talking about powerup settings, but I couldn't explicitly find a reset signal) OR 2. Is there a way to force the FSM's initial state w/o a reset signal at all?  Thanks a lot for your help! Moritz

[Altera_Forum]

Hi, 

 You can generate internal reset for whatever purpose after power up or any time by using basic logic or a small counter.  signal count : unsigned(3 downto 0);  -- to prevent compiler optimising away count attribute keep_count:boolean; attribute keep_count of count :signal is true;  process begin wait until clk = '1';  if count < 15 then count <= count + 1; end if;  if count < 10 then  reset <= '1'; else  reset <= '0'; end if;  end process;  edit: To be on safe side you may also add keep attribute to reset, also make sure that the (power-up don't care) is off so that the count starts at 0 always.

[Altera_Forum]

Thanks for the reply! It looks like an interesting concept (and I guess it works ;)), but shouldn't you somehow have the same problem as with the flipflops storing the state in the FSM with "count" in this code - you don't know what value it has after powerup? 

 edit: oh sorry, I somehow missed your edit there, I will take a look at the attributes...

[Altera_Forum]

Hi, 

 It works and I have used it for several designs. Counter is not strictly a state machine from the compiler prespective, it is based on adder(unlike old style counters which were based on state machine design). The tools guarantee that registers power up low(except those with preset) provided power-up don't care is off in the compiler settings.

[Altera_Forum]

But shouldn't I then be able to manually encode the FSM's reset state to all zeros so that it would come up in that state after powerup using the attributes you mentioned (I guess this somehow has to do with the safe state machine "feature", but I don't see why this approach would not work). Or is it just "cleaner" to generate the reset and then use it for the FSM? 

Have a good start to the new week! Moritz

[Altera_Forum]

Hi Moritz, 

 If you have this reset then you can use it for any task including applying it to the FSM at power up. You can also apply it at run time if things go wrong by (forcing the counter back to zero in the above construct and in this case don't need the keep attribute). As such there is no need to worry about encoding the FSM manually. Your idea makes sense but I am not sure about how compilers treat the registers of FSM(as opposed to other general purpose registers) .