Failed to Enumerate Stratix IV GX FPGA Development PCIe Board on PCIe 3.0 Bus

[Altera_Forum]

I have one Altera Stratix IV GX FPGA Development Board (PCIe based) and want to develop Altera PCIe Linux Custom PCI Driver to access Memory Read/Write Operation (SGDMA) through that PCI driver. 

 I have connected that board in one core 2 duo system which has support of PCIe 2.0 bus and that device enumerated successfully without any issue in Windows as well as in Linux System. But When I connected that same FPGA board in Intel core i3 or i5 system which has PCIe 3.0 bus support at that time system can not able to detect Altera FPGA device as PCIe device and failed to enumerate it in Windows as well as in Linux System.  Does any one has idea about this issue or anyone has faced this type of issue before?  Is there any change required in FPGA design point of view to detect that FPGA board in PCIe 3.0 bus?  Please let me know as soon as possible..  Regards, Ritesh Prajapati

[Altera_Forum]

Does anyone has faced this type of PCIe 3.0 bus enumeration failed issue for Stratix IV GX FPGA Development PCIe Board in windows/linux system? 

 I have downloaded compatible sof file in bios mode and than exit bios mode and wait to start system but still failed to detect board in my windows as well as linux system.  Regards, Ritesh Prajapati

[Altera_Forum]

Sounds like you had a good idea to download the .sof in BIOS mode ... there is an inherent race condition if the FPGA has to load and be ready when the slot reset is deasserted. I had problems with that and one powered up and FPGA loaded, I had to do a worm restart of Windows which if you are lucky, will not cycle the power, just reset the slots and re-enumerate the PCIe buses.

[Altera_Forum]

--- Quote Start ---  Sounds like you had a good idea to download the .sof in BIOS mode ... there is an inherent race condition if the FPGA has to load and be ready when the slot reset is deasserted. I had problems with that and one powered up and FPGA loaded, I had to do a worm restart of Windows which if you are lucky, will not cycle the power, just reset the slots and re-enumerate the PCIe buses.  --- Quote End ---    Hi bob_dixon,  Thanks for reply.  I had load FPGA system (.sof) file in PCIe 2.0 bus system (core 2 duo) from bios mode and just save & exit from bios which works fine without any issue. But whenever i tried to did the same thing in PCIe 3.0 Bus system at that time Device failed to enumerate in windows as well as in Linux System.  Do you have idea or solution for this type of issue?  Regards, Ritesh Prajapati

[Altera_Forum]

I have attached the Stratic IV GX transciever spec section ... it doesn't say anything about Gen3 . 

 There can still be some items to check.  1. The .sof ... need to trace that back to a design that will say how the Stratic IV GX is being configured.  2. If the Stratix IV GX component is somehow configured to be running at Gen3 speed, some Gen3 systems ( slots ) my not support the number of lanes. In theory , a Gen3 slot should be able to scale back from X8 to X4 to X1 , but this may be an implementation specific issue and the Gen3 slot may for example only support X16 expecting that any Gen3 EP will be a graphics card and X8, X4 or X1 can just use a Gen2 slot.

[Altera_Forum]

Hi Bob_dixon, 

 Thanks for reply.  So, you mean there is something from development point of view in FPGA system to configure Stratix IV FPGA board in PCIe 3.0 slot. correct?  I have also tried some other Graphics Cards which can be detected successfully on same PCie 3.0 slot.  Can you please give me some clue from FPGA design point of view to configure this board in PCIe 3.0 slot? Do you have any idea for that?  Regards, Ritesh Prajapati

[Altera_Forum]

Ritesh, 

 Normally if you had a kit , there would be some example projects that run in Quartus ... the function is typically captured in a tool , QSYS, that  allows the various IP blocks to be configured ... ie for PCIe , do you want to configure as X1, X4 or X8 lanes and at Gen1, Gen2 or Gen3 speed if supported. The QSYS system can then generate the Verilog or VHDL ( RTL ) . Once you have the RTL, synthesis will run resulting in the .sof file that configures the FPGA elements to perform the design function.  I will look up the Stratix IV kit .pdf's and attach pointers to them.  Best Regards, Bob.

[Altera_Forum]

Ritesh, 

 This is where I would start.  http://www.altera.com/products/devkits/altera/kit-siv-gx.html  That URL contains everything but still says it supports PCIe Gen2 X8 ... I didn't see any mention of Gen3 speed.  Were you able to determine where the .sof came from ?  Best Regards, Bob.

[Altera_Forum]

--- Quote Start ---  Ritesh,  This is where I would start.  http://www.altera.com/products/devkits/altera/kit-siv-gx.html  That URL contains everything but still says it supports PCIe Gen2 X8 ... I didn't see any mention of Gen3 speed.  Were you able to determine where the .sof came from ?  Best Regards, Bob.  --- Quote End ---     Hi Bob_Dixon,  Thanks for reply.  We have taken one sample Qsys design for stratrix IV Board and started development for our requirements.  Regards, Ritesh Prajapati