Failed to closure timing in building the "pcie-gen4" example in Agilex F-Series FPGA Installer pkg

[seanw_skhms]

I am trying to build the "pcie_gen4" example design provided in the "Intel Agilex F-Series FPGA Installer Package, ES-3V", which I downloaded from https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-agf-fpga.html?wapkw=agilex%20f-series%20development%20kit, and failed in closure routing timing errors.

There are a few of issues found,

1) the example design was created using Quartus v19.4 and targeting to the -E2V device. But I am using the Quartus v20.2, and my development board has -E3V device installed. So I ran the upgrading command when opening the example project, but failed in upgrading the qsys file because of the wrong "associatedclock" and "associatedrest" names made in upgrading the PCIe EP IP. 

2) after fixed the errors in upgrading, I can finish the synthesis and fit processing, but received large slack setup timing error (about 1-2 ns). I switched the device back to -E2V, and the timing error is getting smaller (about  0.5ns), but is still there. The timing error is mostly located inside of the "pcie_bar_interpreter" IP, where it uses the 512 bit wide bus and 350Mhz clock. (also, there are about 58 comb-loop warnings are reported in this IP).

Why I see the errors, but the original example design did not. What should I do in order to fix the timing error?   I tried changing the syntheses settings, but no-help.

I am trying to reduce the bus width from 512bit to 256bit by changing the PCIe EP IP from 16x1 to 8x2 mode (x8 meets our requirement), but I could not find the 256bit wide of PCI-DMA and PCI-Bar-Interperter IPs.

I wonder if Intel could upgrade the examples folder in the installer package using the latest Quartus v20.2 tool and targeting to the right speed grade device? and also provide the example IPs for 256 bit wide PCIe-DMA and PCIe-Bar-Interpreter IPs? 

Thanks,

Xiao

[seanw_skhms · Accepted solution]

Sorry, I was wrong. Actually, the timing error is located in the mm_interconnect modules which are auto inserted by the tool. I missed the parameter settings in the original design for these interconnect modules. After I corrected the pipe-stage parameter setting in these interconnect modules, The routing timing error is fixed.

[SengKok_L_Intel]

Thank you for the update, and this is glad to see the problem is resolved.

Just for your information, for the PCIe P tile example design, you can also generate it from the PCIe IP GUI, and it is timing clean. Thanks.

Regards -SK

[SengKok_L_Intel]

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