Fan-out too weak to trigger SignalTap II ??

[Altera_Forum]

I set up two instances in signaltap, one instance contained a signal that would trigger acquisition at rising edge, the other instance contained the same signal but would be triggered by something else. The problem is the former instance wasn't triggered at all during the runtime while several rising edges on that signal was recorded in the latter instance. The signal was a combinatorial bus, so is it possible to have a situation where the combinatorial fan-out is too weak to trigger the signaltap? If this is not supposed to happen, what could be the reason for this? 

 Thanks!

[Altera_Forum]

What is the sampling frequency of the first instance? Is it enough to capture the rising edge of the signal?

[Altera_Forum]

Hi zoomkrupesh, I used the working frequency for both instances. It seems I can only select a clock signal instead of typing in a frequency manually. Is this the correct way to do it?

[Altera_Forum]

Yes, you need to select clock signal instead of typing frequency manuallyYou can generate higher frequency clock using PLL for debug purpose only. For example,if your design is working at 50MHz clock frequency,you should create a clock of at least 100MHz frequency using PLL and this clock should be used as a capturing frequency.

[Altera_Forum]

Thank you zoomkrupesh. After setting up an additional PLL for signaltap with frequency that is twice as fast as the working frequency, I had a setup violation on a path from a node in my design to a node in signaltap module.  

I'm not sure why there's clock domain crossing here since my understanding is that the second, faster clock is for signaltap sampling only and does not interfere the main module. Any suggestion?

[Altera_Forum]

--- Quote Start ---  Thank you zoomkrupesh. After setting up an additional PLL for signaltap with frequency that is twice as fast as the working frequency, I had a setup violation on a path from a node in my design to a node in signaltap module.   --- Quote End ---   You can assign false path between signal tap sampling clock and your design clock.    --- Quote Start ---   I'm not sure why there's clock domain crossing here since my understanding is that the second, faster clock is for signaltap sampling only and does not interfere the main module. Any suggestion?  --- Quote End ---    Off course there will be clock domain crossing between signal tap clock and your design clock.Whatever node or signals you add in your signal tap file is generated on your design clock which is sampled by signal tap clock.