Feeding an input of a PLL with the output of another PLL - Problem

[Altera_Forum]

Hi! 

 I have the following problem: I want to use a Cyclone 2C5F256 as a LVDS receiver and transmitter. The received data comes from a Cyclone 2C35F484 and is then converted into RS485 signals. The transmitted data goes back to the Cyclone 2C35F484 and even comes from RS485 signals. It´s a kind of Interface Card....   In the Quartus Project I have an ALTLVDS receiver with external ALTPLL and and an ALTLVDS transmitter with external ALTPLL.   The Receiver PLL gets it´s inclock from the LVDS CLOCK (from 2C35 Board).   What I try to do is to feed the Transmitter PLL with the "slow clock" output of the Receiver PLL. I´ll do this to avoid using an extra oscillator on the board.   With this configuration I get the following error message: Error: Can't fit fan-out of node RECEIVE_PLL:inst1|altpll:altpll_component|_clk1 into a single clock region   On an Eval-Board with EP3C40 it worked well. Does anyone know how to solve the Problem? Maybe I have to make some kind of assignement (Global Clock) in the Assignment Editor? Is it a constraint of the EP2C5 ?   I would be happy about every comment!   Kind regards   Stefan

[Altera_Forum]

It doesn't work. Cyclone II PLLs can only be clocked from one of four dedicated clock inputs, each. But you should be able to use a common PLL for LVDS RX and TX.