Filtering PLL power with feed-through capacitor

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Filtering PLL power with feed-through capacitor

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I'm thinking about filtering VCCA_PLL and VCCD_PLL powers in Stratix IV GX with this feed-through capacitor: Murata NFM18PS105R0J3D.

Because of board real estate constraints I'd like to feed NFM directly from core voltage plane (VCC=0.9V) for VCCD_PLL and 2.5V plane for VCCA_PLL. And connect "output" of NFM directly to appropriate FPGA pad. Power planes are well decoupled with x2y and standard capacitors.

Does anyone see any potential problems with such configuration?

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