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Flash Loader IP not loaded on device 1

HAlex
Beginner
153 Views

Hello

 

I am using EP4CGX150CF23C8N with EPCQ128ASI16N flash as AS a configuration device.

When I am trying to program jic file to the flash IC with Intel USB blaster  II - I immediately get message:

"Flash Loader IP not loaded on device 1" and operation fails.

Reducing speed of USB blaster II to 16Mhz (from default 24Mhz) with jtagconfig solve this issue.

The problem is also that USB blaster II running on 16Mhz is somehow ~3times slower than Terasic USB blaster running on 6Mhz (Terasic's blaster programming my flash without any issue).

I don't think that it is a signal integrity issue as sof file downloaded properly and fast with USB blaster II running on 24Mhz.

Also FPGA configured properly from flash device running on 40Mhz.

So why jic file programming fails with USB blaster running on 24Mhz?

 

Thank you

 

Alex

 

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6 Replies
NurAiman_M_Intel
Employee
124 Views

Hi,


The Intel® FPGA Download Cable II has a default TCK frequency of 24 MHz. However, it is mentioned in the Userguide that for some, signal integrity and timing prevent operating at 24MHz. Hence we recommend to lower the TCK frequency of the download cable. You may refer to below UG.


https://www.intel.com/content/www/us/en/docs/programmable/683719/current/changing-the-tck-frequency.....


Regards,

Aiman


HAlex
Beginner
114 Views

Hello

 

As I wrote I did performed reduction of the operating frequency to 16Mhz but even with this frequency USB blaster II working much slower than Terasic USB blaster running on 6Mhz. This cause us difficulties using USB blaster II in mass production (and we don't have enough Terasic USB blasters).

Anyway, I am not sure that the issue is a signal integrity (unless it is inside FPGA). This is because JTAG path running on 24Mhz configuring SOF file without problem. 

And the path between FPGA and flash running on 40Mhz configuring FPGA smoothly.

Maybe the problem is with SFL IP that can't run on 24Mhz??

What do you think?

 

Thank you

 

Alex

NurAiman_M_Intel
Employee
102 Views

Hi Alex.


The JTAG line to FPGA might not have signal integrity issue, that's why you can successfully program .sof file.


However, the line between JTAG to flash might have signal integrity issue. Hence that is why you need to reduce the TCK frequency.


Please check the routing from JTAG header to flash. Also, check your board layout to make sure there is no SI issue.


Make sure you refer to EPCQ-A configuration datasheet.

https://www.intel.com/content/www/us/en/docs/programmable/683818/current/epcq-a-serial-configuration...


Regards,

Aiman



HAlex
Beginner
94 Views

Hello

 

JTAG connector is not connected directly to the flash, it is connected to FPGA only and serial flash loader is used to program the flash.

The connection is done according to a following schematics:

HAlex_0-1674032591468.png

As I wrote also FPGA configuration from the flash running in 40Mhz is done correctly.

All nets between JTAG - FPGA and FPGA - flash are handled very carefully and matched in length with reference to TCK/DCLK.

So personally, I suspect that the problem is with SFL IP (it can't work in 24Mhz or not initialized and etc...)??

Also, why USB blaster II running on 16Mhz is much slower than Terasic running on 6Mhz?

  

Thank you

 

Alex

NurAiman_M_Intel
Employee
69 Views

Hi Alex.


  • How long is the timing when using USB Blaster and Terasic?
  • Have you try to use another USB blaster? Is the timing still slower?
  • Can you provide us your schematic, from the same part as the screenshot you just shown?


Regards

Aiman


HAlex
Beginner
50 Views

Hello Aiman

 

1. Programming same jic file with:

USB blaster II running on 16Mhz (after I run: jtagconfig --setparam 1 JtagClock 16M) - 3 minutes 39 seconds. 

Terasic USB blaster (running on default speed, should be 6Mhz) - 56 seconds.

2. Don't have another Altera USB blaster II for compare.

3. 

HAlex_0-1674380381638.pngHAlex_1-1674380418935.png

Micron flash is not assembled.

 

Thank you

 

Alex

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