FPGAs contain D flip flops (registers) and when you want other types you typically achive this with feedback and/or combinational logic. Now when you design you normally don't think in terms of flip flop types but rather functionality and you let the synthesis tools determine the implementation.
A T flip flop is just a D flip flop with the output fed back to the input through an inverter. An SR flip flop is just a D flip flop with control over the setting and reseting which I typically do using if and else if statements in verilog. Not sure about JK since I can't remember what a JK flip flop does (again I don't think in terms of flip flop types so I've never had to care what a JK is).
I recommend taking a look at the code templates built into Quartus or the synthesis optimization guide for Quartus to see examples of what I'm talking about.
