Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Fmax for a block

Altera_Forum
Honored Contributor II
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Hi everyone, 

 

I am wondering how to find an Fmax for an always block to work correctly. I have an always block work fine at 25MHz, which returns incorrect values at 50MHz.
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Altera_Forum
Honored Contributor II
338 Views

Use TimeQuest to put timing constraints on the design. 

 

Use the RTL and technology viewers to look at how the logic was implemented. 

 

25MHz and 50MHz are very slow, you should have no problem meeting timing if your logic is correct. 

 

Cheers, 

Dave
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Altera_Forum
Honored Contributor II
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Unless it contains very long logic paths...

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