- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
How do i write for i= 0:63 :360 (matlab code) in VHDL .searched for long about for loops but couldn't see any instance of the above form. Is defining an array and writing "for in A"the only way??
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- ... for i= 0:63 :360 (matlab code) in VHDL ... --- Quote End --- Did you choose purposely an increment that doesn't match to the exit condition?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
@jb123 : I didn't get you
I have to use array values corresponding to those indices(i=0:63:360) M(i ) := blah blah- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Sorry, but I'm very poor at matlab.
Does your example evaluates in the following: for i = 0, 63, 126, 189, 252, 315 : the loop body is executed i = 378 : the loop is exited Do you have to compare i to 360 instead of 378?- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
in VHDL, the loop variable is an integer if you use a for loop:
for i in 0 to 63 loop
end loop;
will loop 64 times. for a while loop, you can do whatever you want:
variable i : real : 0.0;
while i < 1.0 loop
....
i := i + 0.001;
end loop;
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
NB: while loops are not usually synthesisable.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
@jb123 yes that is what i have asked; at few places in my code i have to deal with large integers like 0:64 :10000 , i can't keep giving values; i think i have to create a loop to define a array as such and then gave the array range to the for loop ;
Correct me if I am wrong; @Tricky : How do i use a constraint without using a while loop? any alternative loop which can be synthesisable and serves the purpose??- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The way to start thinking about this - stop thinking about loops and code constructs and think about what the underlying circuit should look like. VHDL stands for VHSIC Hardware Description Language. The key word there is description as VHDL is used for describing a circuit. Without understanding the circuit, how do you expect to write the VHDL?
Matlab -> VHDL is not a straightforward conversion.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Okay. I know what the circuit does. I will be able to write it in vhdl. But can you refer me an article which says synthesisable loops and packages so that i would not commit mistakes again.Please
Thanks for helping me all through this- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
For synthesis, for loops will unroll into parallel hardware. and if you need a while loop you're doing something wrong and clearly dont understand the circuit.
I suggest drawing the circuit out (on paper, or MS visio or similar) before writing any VHDL.- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page