Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

Arrays-VHDL

Altera_Forum
Honored Contributor II
2,059 Views

1.In arrays(of real type ) how are we supposed to find the maximum value index in the array?I think A'HIGH is something different which gives the highest subscript of the array.What's the difference between A'HIGH and A'RIGHT (low to high indexes).? 

 

2. How to find the index of the values in a array which are less than a particular value or a constraint like that. I mean find(MP2>0.77)(IN matlab); 

 

Please help me :)
0 Kudos
8 Replies
Altera_Forum
Honored Contributor II
978 Views

 

--- Quote Start ---  

1.In arrays(of real type ) how are we supposed to find the maximum value index in the array?I think A'HIGH is something different which gives the highest subscript of the array.What's the difference between A'HIGH and A'RIGHT (low to high indexes).? 

 

2. I have to find the index of the values in a array which are less than a particular value or a constraint like that. I mean find(MP2>0.77)(IN matlab); 

 

Please help me :) 

--- Quote End ---  

 

 

I've attached a source code that should solve your request as I understand it. 

 

As far as vectors with ascending indices are of concern, there is no difference between 'high and 'right.
0 Kudos
Altera_Forum
Honored Contributor II
978 Views

1. It depends how you declare the array: 

 

signal a: some_array_t(0 to 7); 

signal b : some_array_t(7 downto 0); 

 

a'high = 7; 

a'right = 7; 

 

b'high = 7; 

b'high = 0; 

 

does this makes sense? 

 

2. you'll have to write a function to do it  

NB - Real type is not synthesisable - so I assume this is all for testbenching.
0 Kudos
Altera_Forum
Honored Contributor II
978 Views

Thank you very much for your effort JB123;(my dot button doesn't work,both of them luckily :D) I expected it to have some command as in matlab; I suppose that i have to write the code for my second question too; Thanks again

0 Kudos
Altera_Forum
Honored Contributor II
978 Views

2. you'll have to write a function to do it  

NB - Real type is not synthesisable - so I assume this is all for testbenching. 

--- Quote End ---  

 

 

here I have to deal with real type numbers and this is to be implemented; So how to make it synthesisable ??
0 Kudos
Altera_Forum
Honored Contributor II
978 Views

forget real types for implementation. 

For floating point you need to use the flaoting point cores from the altera IP library. But usually you can use fixed point. You only need to use floating point in extreme cases. I suggest a re-design using fixed point as that is essentially integer arithmatic that FPGAs are good at.  

 

Basically - transistion from MATLAB to FPGA is NOT a simple task.
0 Kudos
Altera_Forum
Honored Contributor II
978 Views

Maybe you wan't to do the transition from real to fixed point in matlab. 

There should be something (in the fixed point toolbox) named "fixed point objects" 

 

Doing that you'll can do the validation of certain fixed point resolutions in matlab. 

 

After you've implemented the above in HDL an ecquivalency check against your matlab 

results is sufficient for verification, which is a huge advantage, because you can have 

your computer do it for you. 

 

Since VHDL2008 there should be fixed point and floating point type packages. 

The libraries are free for download (google should do the trick). 

 

I've no experience with that libraries except that I've successfully compiled an example 

with QII a long time ago.
0 Kudos
Altera_Forum
Honored Contributor II
978 Views

@Tricky : Fine i will start correcting the code to use fixed points; what inbuilt standard packages can i use??ieee_proposed.fixed_pkg.all;,is this package synthesisable?? Can you refer me a ebook or article about synthesisable packages; I have stopped using math_complex(came to know that it is also not synthesisable) and defined every operation of complex package in my code;

0 Kudos
Altera_Forum
Honored Contributor II
978 Views

@jb123 I have found some synthesisable packages at this link; just wanted to share if someone needs them like me :) 

http://www.eda-stds.org/fphdl/ 

I will look into things which you suggested about fixed point tools;
0 Kudos
Reply