Found a bug related to non-contiguous bus slices? Confirm / deny

[Altera_Forum]

Ok, I am curious if this is a reproducible bug for others or if there is something unique about my project settings. 

 1. I have a .qsf file that defines all my pins. I have a bank of 8 pins named EXTGPIO[0] through EXTGPIO[7] defined in that qsf. 2. My top level document is a bdf. On that BDF I defined output pins for EXTGPIO[4] and EXTGPIO[6] (but none of the other signals in that bank were instantiated on the BDF). 3. Compile the project. Project compiles but I get critical warnings that those two pins are "not assigned to an exact location on the device". The generated sof fails to drive either EXTGPIO[4] or [6].  4. Open the BDF and the QSF. The BDF has the corresponding pin numbers defined in the QSF file but still no luck compiling working code that drives those pins.  After 1.5 days of head scratching and poking, we discovered the bug mysteriously goes away if you define the other pin between those two pins. In other words, you have to use a contiguous range of pins.   So just adding a pin definition for EXTGPIO[5] and grounding it makes the critical warnings go away and makes the code drive EXTGPIO4 and EXTGPIO[6] correctly.  After further poking, the problem is reproducible for any combination of pins I tried. If I tried a contiguous slice, compiled fine and drove the pins just fine. But if I omit any pin in the middle of a range to make it non-contiguous, I get critical warnings and cannot drive the pin.  Can anyone independently confirm this? For my project I confirmed it happens on 9.2sp2, 10.0sp1, and 10.1.  Thanks, David