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I am making a circuit that needs a delay block. The clock frequency is 1MHz and I want the delay block to send a HIGH signal after about 10ms so basically I shall have to divide the frequency by 10000 or something. Any Ideas?
What I have done is to make a 7 bit counter and a 3 bit counter so four 7 bit counters and one 3 bit counter connected in series gives me delay of a little more than 10ms. The thing is that the computer gives the message of Clock Skew because the out of the first counter goes into the clock of the second and so on, so the first counter has a clock input but the succeeding counters only get the output of the previouse counter. The output of the Delay block is not used anywhere else except that it is used to enable the state of a state machine to move on to the next and soon the counters in the delay block are reset. Any ideas of making a better good Delay block to get 10ms delay from?Link Copied
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--- Quote Start --- What I have done is to make a 7 bit counter and a 3 bit counter so four 7 bit counters and one 3 bit counter connected in series gives me delay of a little more than 10ms. --- Quote End --- This would be a solution for breadboard circuit with TTL or CMOS counter ICs to achieve a minimum part count. With programmable logic, it's appropriate to build a single synchronous counter. You can generate a counter to 10000 with the MegaWizard or write a few lines of HDL code. The Quartus Editor has VHDL and Verilog design templates for counters, you can easily change it to a 10000 counter. In situations, where a divided clock is necessary, use a clock enable rather than a divided clock. The first counter generates a overflow/carry signal, that is active for one period of the input clock. The cascaded counter gets the same input clock (=system clock) and the overflow as a clock enable. This way, you can cascade counters synchronously without timing issues.
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Sounds like your counters are asynchronous. If you use synchronous ones you'll probably find life a whole lot easier.

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