Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Frequency of DCLOCK

Altera_Forum
Honored Contributor II
‎08-16-2010 06:44 AM
1,407 Views

Hi, 

I am using ARRIA II GX FPGA with MAX II CPLD. For Active Serial and Fast Passive Parallel (FPP) configurations, what should be the frequency of D_CLK? 

On what other factors will this clock frequency depend?
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Altera_Forum
Honored Contributor II
‎08-16-2010 08:24 AM
417 Views

It's in the datasheet. Before designing with FPGAs, check the datasheet first. 

 

Good luck with your design, Ton
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