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Hi,
I'am so sorry if there are some mistakes in english. I try to modify the frequency of StratixIV (used the PLL in SOPC builder), always, i obtained with the clock tools the same frequency 100Mhz. I see that's abnormal problem. Any suggestion please :(.Link Copied
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--- Quote Start --- NO I meant in the RTL viewer. What you are seeing is only the top level view. To find the pll you will need to go down the hierarchy by looking inside the SOPC component. You can also try to find it in the tree (tree list on the left of the rtl view). --- Quote End --- Ah ok; think you very much Daixiwen.:)
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--- Quote Start --- Uncomment the line "derive_pll_clocks -create_base_clocks" in pll.sdc and add in pll.sdc to your project through Quartus Assignments->Settings->TimeQuest Timing Analyzer and add the timing file. Let me know how this works. --- Quote End --- Hi protocol Enginner, Finally it work, i bought license. And i try to calculate the time with alt_timestamp() function:).

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