Hi ,I am working on a design , it has a top level VHDL file ( a main state machine in it) and then a UART is enabled from this Main ( State machine ) . Everything works fine in RTL simulation . But when i switch to Gate-level Simulation i dont see any response or even glitch when UART is enabled . This is using Quartus-II ver 10.0 and Altera-Modelsim . When i compiled the design in Xilinx , again it failed in Gate-level but before shutting down it spite out a message about Modelsim couldnt handle 10K lines of code . Any clues ??? Thanks in advance.
In Gate Level it wont start , not even show any glitch . Just stay dorment .I have traced the enable signal , it is valid but the UART State machine wont kick start .
What is that doesn't start?Modelsim? The Uart? The FSM? If Modelsim starts, do you see the input signal that switch? Do you see the outputs of the FSM that switch?
The RTL simulation screenshots you've posted don't cover the same time frame as the gate-level simuation screenshots.Also, I'd also suggest that you take a good look at the uut input and output signals, in order not to hide any missing connections For example, I don't a /tb_ssi/uut/clk signal in the simulations. I guess it's problably the same signal as one of the /tb_ssi/clk* signals, but I don't know which. This makes it impossible to compare your results.