Gated Clock + Clock MUX-> what primitives to use?

[Altera_Forum]

Hi All, 

 As for the Gated Clock implementation -> what primitives to use?   Could someone provide examples?   Thank you!

[Altera_Forum]

If you want a reliable design, don't use gated clocks. FPGAs aren't designed to support them. 

 Solve it another way. Use your clock gating control signal to determine what the logic should do when it's active (clock disabled).  Cheers, Alex

[Altera_Forum]

Yes, use clock enable control instead of gating the clock. Also, you can add in the clock control block (ALTCLKCTRL) and use its enable signal to disable a global clock.

[Altera_Forum]

--- Quote Start ---  Hi All,  As for the Gated Clock implementation -> what primitives to use?   Could someone provide examples?   Thank you!  --- Quote End ---    Never ever gate clocks, clocks may not be multiplexed. Here yopu will find what you need: https://www.dropbox.com/s/8z2rgxvisni71y6/syncdesign2.pdf?dl=0