Gates are not appeared in RTL viewer

Altera_Forum · ‎07-10-2011

Hey all,

I wrote the next code:

module increase_duration_1(in, clk, out, reset);

parameter LEN=10;

input in,clk, reset;

output out;

wire [LEN-1:0] or_out,path;

wire rstn;

or U2(or_out[0],path[0],path[1]);

assign out=path[LEN-1];

assign path[0]=in;

not not1(rstn,reset);

genvar i;

generate

for (i=0; i<LEN-1;i=i+1)

begin: shift_reg

dff u( .clk(clk),

.d(path),

.q(path[i+1]),

.clrn(rstn),

.prn(1'b1));

end

endgenerate

generate

for (i=1; i<len-1;i=i+1)

begin: or_connections

or u3 (or_out,or_out[i-1],path[i+1]);

end

endgenerate

endmodule

attached photo shows what I get in RTL viewer. why I don't see logic gates?

what am I doing wrong?

Thanks in advance

Altera_Forum · ‎07-10-2011

The or gates are ignored, because they don't generate any output signal in your design.

Altera_Forum · ‎07-10-2011

Or gates generate or_out[i].

and what is about not gate?

Altera_Forum · ‎07-10-2011

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Or gates generate or_out[i].

--- Quote End ---

or_out isn't an output of your design. out is the only one, wired to the DFF chain output.

Altera_Forum · ‎07-10-2011

Thank you very much, now I have OR gates.

What is about the NOT gate. his output is connected to CLRN of DFFs and input to RESET. Why I don't see him?

Thanks

Altera_Forum · ‎07-10-2011

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What is about the NOT gate.

--- Quote End ---

Look sharp, it has been simply absorbed by inverting the signal. But this doesn't mean much, because RTL is just a functional circuit. You have to review the synthesiszed netlist to see how the cicruit is implemented in LEs.