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Valued Contributor III
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Generate 10 phase clock for 10 ADC from Cyclone III - Is it possible?

Hi,  

I want to ask more you experienced, 

is it possible with Cyclone III to generate clock for 10 ADCs (by 1/10 phase) at 100MHz so total sample rate will be 1GSps, it act also as data buffer, or I'll need any external CPLD to generate clock ?
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Valued Contributor III
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No. I'm not aware of a CPLD that will do that for you either. 

 

Just to clarify - you're trying to generate 10x 100MHz clocks, shifted by 1ns each? 

 

Cheers, 

Alex
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Valued Contributor III
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It should be possible  

At least in Hantek DSO is Cyclone III with MAXII (clock is generated from that MAXII) and they do 1GS from 8 ADC so they must generate 8x 125MHz shifted by 1ns
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Valued Contributor III
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Forgive me for saying but if you are aware of a design that successfully does this - why ask the question? 

 

MAX II devices do not have PLLs. So they will not be responsible for generating the clocks you mention. If the clocks are routed through the MAX II, having been generated elsewhere, then I'd question the resulting phase accuracy. 

 

Cyclone III PLLs can only generate 5 output clocks. Whilst it will happily generate 5x 100MHz clocks, shifted +1ns each, you clearly need 2 PLLs to solve 10 clocks. Fine. However, you'll have great difficulty ensuring an accurate phase shift between the two PLLs. So, you'll end up with two sets of five clocks, accurate to each other but very likely to be shifted with respect to each other. This shift maybe small and possibly small enough to allow a solution. 

 

Cyclone V PLLs support 9 output clocks. So, conceivably you could generate 10 phases, as you need, by using the source clock in addition to the 9 PLL output clocks. However, you will still have trouble accurately controlling the phase of the 9 output clocks with respect to the source. 

 

The Stratix & Arria families offers PLLs with more (18) output clocks. If I was looking to solve this, I'd be looking to these families. 

 

Cheers, 

Alex
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Valued Contributor III
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They use clock from Cyclone (my fault) but they use other components out of specification and with lot of noise  

I want to know it is there any recommended solution or is better to use external clock generator
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Valued Contributor III
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Use and external clock generator. 

 

There are a serious issues in trying to use multiple outputs from a single PLL to drive circuitry outside the FPGA. Typically, only one of the PLL's output clocks is intended for routing to an external pin. The others are intended or use inside the FPGA and the routing resources in the FPGA are designed to support that. 

 

If you start pushing multiple clocks from the PLL to pins the FPGA will use routing resources that that ae not ideally suited. This will introduce very varied delays meaning any phase relationship you specified at the output of he PLL will be compromised. Worse still, each time you route the FPGA these delays will change - unless you're able to lock down certain resources specifically, which will prove to be difficult. 

 

Read through chapter 5 - "clock networks and plls in the cyclone iii device family (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyc3/cyc3_ciii51006.pd...)" of the Cyclone III handbook. Table 5-3 and figure 5-6 show the Cyclone III PLL. One Dedicated clock output is the important bit here. 

 

Cheers, 

Alex
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Valued Contributor III
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But in part about clock output they say: 

"Other output counters can feed other I/O pins through the GCLK."
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Valued Contributor III
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Yes - indeed you can. However, the GCLK network is a set of low latency paths intended to clock the internal logic of your FPGA. Depending on the part you use you'll have 10 or 20 GCLK resources available to you. If you use these up simply routing PLL clock output phases (that aren't used inside the FPGA) to I/O pins, then you will run out of these resources quickly. Depending on how full your FPGA is this could cause Quartus difficulty in fitting your design and making it meet timing. 

 

 

--- Quote Start ---  

Only the C0 output counter can feed the dedicated external clock outputs. 

--- Quote End ---  

This is a low latency path whose delay will differ from any other PLL output clock phases routed to I/O via GCLK. So, you may end up with a set of clock signals whose relative phases aren't quite what you want. 

 

If you're careful - yes - this could all be made to work. However, if it were me, I'd use an external clock generator. 

 

Cheers, 

Alex
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