Generate programming file for multiple device chain (HDL and Nios code)

[Altera_Forum]

I have a board that has two Cyclone IV devices on it. Each Cyclone will have it's own unique HDL and embedded NIOS processor. My question is how do I generate the programming file for the serial configuration device that will program both devices on power-up? Note, this is not a hardware design question - I have already designed the circuitry in accordance with Altera's documentation - it is a generate the programming file (in Quartus, in a shell, in Eclipse, etc.) question. 

 I believe I've found a possible example on how to generate a file for one chip (http://www.altera.com/support/kdb/solutions/rd04112006_450.html). What is the process for adding a second one? Do you just add the SOF and ELF data for the second chip after the SOF and ELF data for the first?  Thank you.

[Altera_Forum]

Do I assume you've captured a design implementing a 'Multi-Device AS Configuration' scheme, as found in the configuration handbook - Figure 8-3? Page 8-13. 

http://www.altera.co.uk/literature/hb/cyclone-iv/cyiv-51008.pdf (http://www.altera.co.uk/literature/hb/cyclone-iv/cyiv-51008.pdf)  Whilst this is designed to configure multiple devices from a single configuration device, I'm not sure how you can (easily) retrieve two separate software images for your two Nios' in two separate FPGAs. I don't think it's going to be as easy as adding a second set of .sof & .elf files to the config device. There's quite an amount of arbitration to consider to prevent both devices accessing the configuration device at the same time.  Like I say, it can be done. Let me know whether I've interpreted your question correctly.  Regards, Alex

[Altera_Forum]

Yes, that is the blueprint I followed for the hardware design. Perhaps I hadn't thought this through completely. You give the impression that it would be a rather tedious operation to pull this off. Are there any resources online you know of that discuss this? (other forums I may have missed, etc.?) What approach would you recommend if you were tackling this issue? 

 I guess I don't absolutely need a NIOS in the second Cyclone device (although it would make things much easier). In this configuration, is generating the program file as easy as putting the second SOF after the main SOF and ELF files?  Thanks again

[Altera_Forum]

No you will have to put the two sof files one after the other, it is the only way both FPGAs will read their respective configurations. In this mechanism, the slave FPGA will attempt to read its image just after the master FPGA is finished reading its own, so if you put the elf file between the two images the second FPGA won't configure itself. 

 Then there is the problem of the Nios CPUs. The first FPGA is the only one capable of driving the EPCS in application mode. Besides the default bootloader embedded in the EPCS controller will jump over the first sof image and will try to read the software application there. In your case you will need to write a specific bootloader that will be able to jump over both images. If you need a Nios in the second FPGA you will also need a specific bootloader, but you will still need to use the first FPGA to read into the EPCS so you will need to implement a means of communication between the two FPGAs.

[Altera_Forum]

In the Xilinx world, the FPGA image would contain a block ram that is initialized with reset vectors and boot code for the soft core processor. I'm new to Altera, so I don't know if this is possible here. Assuming it is, then your EPCS would simply have two FPGA images programmed.