Generating a signal (a VHDL description) with a well-defined frequency in a FPGA

[Altera_Forum]

Hello,  

In fact, I'm working on a project that aims to put a communication platform to interact with hydrogen sensor wirelessly. The platform consists of an evaluation board from Xilinx ML505 (on which there is a Virtex 5) which will implement the baseband digital processing and another board (Software Defined Radio) for the analog front end that includes the blocks needed (modulator / demodulator, filter, LNA, PA, local oscillator) to communicate on the UHF band (900 MHz). The platform requires a 12-bit DAC and an ADC 12-bit to adapt the two boards. So I need help to generate a baseband signal (VHDL description) with a defined frequency, otherwise, I have trouble to describe the signal generator in VHDL

[Altera_Forum]

--- Quote Start ---   The platform consists of an evaluation board from Xilinx ML505 (on which there is a Virtex 5)   --- Quote End ---   This is an Altera group. You'll need to go and find a Xilinx group for device related help.    --- Quote Start ---   which will implement the baseband digital processing and another board (Software Defined Radio) for the analog front end that includes the blocks needed (modulator / demodulator, filter, LNA, PA, local oscillator) to communicate on the UHF band (900 MHz). The platform requires a 12-bit DAC and an ADC 12-bit to adapt the two boards. So I need help to generate a baseband signal (VHDL description) with a defined frequency, otherwise, I have trouble to describe the signal generator in VHDL  --- Quote End ---    The following has references that will help:  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf  http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf  Also look at the Xilinx DSP book  http://www.xilinx.com/publications/archives/books/dsp.pdf  Cheers, Dave

[Altera_Forum]

If I understood your system; the ADC samples your sensor and then you have to process it and pass it through DAC to 900MHz.  

 And that you want to generate a test signal instead of ADC generated signal to test your baseband processing. In that case you don't need vhdl but just a vector(possibly random) generated off chip, filtered to your expected bandwidth and save to ram. Then when testing you need to read the test signal on the appropriate sampling frequency.

[Altera_Forum]

to dwh 

Hi, I know that is an Altera group but the basics remain the same whether for Xilinx and Altera especially there is a difference in the description language (VHDL vs Verilog). Anyway, thank you for the links, they are too useful to me Thank you.

[Altera_Forum]

to kaz 

Hi, I need the description in VHDL because this subject is a part of my project, otherwise, this is my first approach is used to communicate with a remote sensor, so the internal digital architecture is a transceiver baseband (on the emission chain we will generate a signal to send it to the sensor and in the receiver it will acquire the detection rate of hydrogen from the sensor). But the project goes beyond this approach does, to design a reconfigurable architecture. Thank you

[Altera_Forum]

Your question isn't quite clear. I understand that you are talking about a signal generator in hardware, not in simulation. The possibilities to implement test signals in simulation are basically unlimited. In synthesized hardware, the suitable method depend on the intended signal characteristics, which hasn't been mentioned yet. 

 P.S.: A comment regarding the implementation of an UHF transceiver in FPGA. This is possible of course, but according to the yet revealed details, a 1$ (or so) wireless chip should do the same. It already contains a full featured digital transceiver. Unless you're planning completely new wireless protocols or very specific features, the FPGA solution seems to be a somewhat longwinded approach, but instructive indeed.