Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Genvar: Shift Register

Altera_Forum
Honored Contributor II
‎05-12-2010 01:50 AM
1,546 Views

I would like to implement a set of 32bit shift register using genvar. However, i wonder why the input and output of my block is always 1 bit only instead of 32.  

 

The code is attached.
shift_reg1.v
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Altera_Forum
Honored Contributor II
‎05-17-2010 02:18 AM
646 Views

I have detected the mistake done. The name of submodule to be instantiated is wrong. 

 

thanks
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