Getting a MIF opcode error

[Floppycatman]

Hello,

Trying to reconfig transceiver in my design. As I see in STP alt_xcvr_reconfig function reads from ROM only 20 words but the MIF file is 57 words long.

Hello!

Still trying to reconfig CycloneV GT XCVR. By now I have a project that include XCVR, reconfig, ROM and system console to control the reconfig core.

When I start the streamer I get the MIF opcode error.

Then I perform this commands in system console I getting 0x00, but It should be 0x2 'cause I've already enable 16-bit address mode for reconf core.

master_write_32 $master_path [expr 0x3B*4] 0x1   master_write_32 $master_path [expr 0x3C*4] 0x2   master_write_32 $master_path [expr 0x3A*4] 0x1   master_write_32 $master_path [expr 0x3B*4] 0x1   master_write_32 $master_path [expr 0x3A*4] 0x2   master_read_32 $master_path [expr 0x3C*4] 0x1

So the question is why I can't read the '1' from field MIF address mode? Maybe I setting it the wrong way?

[Deshi_Intel]

Hi Floppycatman,

We don't normally pay attention into the exact words transfer as this should be automated process once user write to the correct register address to pick the right profile for switching.

For instance, with embedded reconfiguration streamer feature enabled in Arria 10 Native PHY IP,

user can Perform a read-modify-write to address x340 with the desired profile select, broadcast bit (applicable for Native PHY only), and configuration load bit set accordingly.

• For example, to stream profile 1 to a channel, perform a read-modifywrite to bits x340[2:0] with 3’b001, bit x340[6] with 1’b0 to disable broadcasting and bit x340[7] with 1’b1 to initiate streaming.

Thanks.

Regards,

dlim

[Floppycatman]

I dunno if this allowed here but up theme with new question.