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Altera_Forum
Honored Contributor I
2,485 Views

Getting rid of some differential I/O pins and PowerPlay warnings

Hello, 

 

I am programming a MAX10 FPGA on Quartus Prime and I got the following warnings: 

 

Critical Warning (16562): Review the PowerPlay Power Analyzer report file (<design>.pow.rpt) to ensure your design is within the maximum power utilization limit of the single power-supply target device and to avoid functional failures. 

 

Warning (176674): Following 2 pins are differential I/O pins but do not have their complement pins. Hence, the Fitter automatically created the complement pins. 

 

To try to solve the critical warning I runned the PowerPlay Power Analizer tool leaving all parameters as they were when I opened it (nothing changed) and for the normal warning I wanted to use two ALT_INBUF_DIFF primitives but they are not supported for MAX10 and I got an error so I do not know how to get rid of this warning. 

 

Do you guys have any idea of how to solve these problems? Thanks in advance! 

 

Regards, 

Javiwolf
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6 Replies
Altera_Forum
Honored Contributor I
199 Views

Just in case this might help to solve my problem, the critical warning has no further info messages (unfortunately) and the warning about the differential signals displays the following messages: 

 

Warning (176118): Pin "LVDS_in1" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LVDS_in1(n)" 

Warning (176118): Pin "LVDS_in2" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "LVDS_in2(n)" 

 

As I cannot create a LVDS_in1(n) input as such (that would generate an error) I am still wondering how I could tell the tool I am using two differential LVDS signals... Is there any MAX10-compatible differential buffer?  

 

Thanks!
Altera_Forum
Honored Contributor I
199 Views

I don't understand. If you're not using differential signaling, why are you using a differential I/O standard? Quartus is looking at the I/O standard you set for the signal on LVDS_in1 and LVDS_in2. If you don't mean to be using a differential I/O standard, change it to a single ended standard in the Pin Planner. Then it won't try to create an n pin for you that you're not even going to be using.

Altera_Forum
Honored Contributor I
199 Views

I understand that you want differential IO. 

 

It's normal operation that Quartus supplements the inverted pin for differential IOs that haven't been explicitly assigned, either check if your schematic connects the right pins or just ignore the warning. In the usual design workflow, the (n) pins would have been assigned automatically along with (p) pins in Pin Planner Tool.  

 

The power supply warning is a "watch your step" thing. Most designers will know before that a single supply MAX10xxSC device shouldn't be run with all logic cells switching at several 100 MHz core clock, or it might run hot. If you're unsure about expectable power dissipation of your design, run PowerPlay.
Altera_Forum
Honored Contributor I
199 Views

I am using two LVDS channels and every channel needs differential IOs so this is why I need the automatically generated negative signals. I was wondering if I could define them in the top module and then use a buffer as people do with other FPGAs by means of the ALT_INBUF_DIFF module (which does not work in MAX10 devices). So I should just ignore the warning and use the auto-generated signals as I implemented them in the Pin Planner Tool, right? That would do the trick but it would be nice if there was a proper way to define the differential inputs on the op module and buffer them to send them as one data signal to the LVDS megafunction (which only accepts a single signal, not differential). 

 

Thanks a lot for your help!
Altera_Forum
Honored Contributor I
199 Views

I don't see an advantage of specify separate positive and negative pins in HDL although it's actually a single differential signal that must use dedicated pin pairs. 

 

After the (n) pins have been automatically supplemented in pin planner, they should have regular pin assignments and don't give a warning.
Altera_Forum
Honored Contributor I
199 Views

The reason why is just to define all my inputs in the top level entity. As I said, there is even an Altera module to handle differential inputs and it helps clearing up that these signals are differential without seeing the Pin Planner. On the other hand, it is not a big issue so I will ignore that warning and leave the design as it is. 

Thanks a lot for your help FvM!