GrayScale from RGB

[Altera_Forum]

Hello everyone i bought the Terasic 5MP Camera to do some image processing inside but i am kinda lost in the Verilog.. 

 For example, i have    // FIFO Write Side 1 .WR1_DATA({1'b0,sCCD_G,sCCD_B}), .WR1(sCCD_DVAL), .WR1_ADDR(0), .WR1_MAX_ADDR(640*480), .WR1_LENGTH(9'h100), .WR1_LOAD(!DLY_RST_0), .WR1_CLK(~CCD_PIXCLK), // FIFO Write Side 2 .WR2_DATA( {1'b0,sCCD_G,sCCD_R}), .WR2(sCCD_DVAL), .WR2_ADDR(22'h100000), .WR2_MAX_ADDR(22'h100000+640*480), .WR2_LENGTH(9'h100), .WR2_LOAD(!DLY_RST_0), .WR2_CLK(~CCD_PIXCLK), I can see that green red and blue channels are there and they are connected to the VGA OUTPUT.  The system is working perfectly well in my DE2, however i want to transform it to a grayscale image instead of RGB  I dont want to use floating points so i will use a simplification like channel = red+2*green+blue  how can i do that in Verilog?? I am really lost..  thanks

[Altera_Forum]

Use the following code: 

 module rgbtoy(r,b,g,y); input [9:0] r,b,g; output [9:0] y;  //y=0.299r+0.587g+0.114b; assign y = (r>>2)+(r>>5)+(g>>1)+(g>>4)+(b>>4)+(b>>5);  endmodule

[Altera_Forum]

hi thanks for the reply 

and i send the Y to the R, G or B vga out pin?

[Altera_Forum]

Sure, send Y to all three outputs R, G, B of VGA

[Altera_Forum]

thanks a lot.. 

what if i want to do some segmentation after that? I will have another block with just one channel and Y going inside right. Do you know any bg subtraction mode or anything like that in hdl?

[Altera_Forum]

how can i retrieve a frame from my camera? 

 That's my top..   always@(posedge CCD_PIXCLK) begin rCCD_DATA <= CCD_DATA; rCCD_LVAL <= CCD_LVAL; rCCD_FVAL <= CCD_FVAL; end VGA_Controller u1 ( // Host Side .oRequest(Read), .iRed(Read_DATA2), .iGreen({Read_DATA1,Read_DATA2}), .iBlue(Read_DATA1), // VGA Side .oVGA_R(VGA_R), .oVGA_G(VGA_G), .oVGA_B(VGA_B), .oVGA_H_SYNC(VGA_HS), .oVGA_V_SYNC(VGA_VS), .oVGA_SYNC(VGA_SYNC), .oVGA_BLANK(VGA_BLANK), // Control Signal .iCLK(VGA_CTRL_CLK), .iRST_N(DLY_RST_2) ); Reset_Delay u2 ( .iCLK(CLOCK_50), .iRST(KEY), .oRST_0(DLY_RST_0), .oRST_1(DLY_RST_1), .oRST_2(DLY_RST_2) ); CCD_Capture u3 ( .oDATA(mCCD_DATA), .oDVAL(mCCD_DVAL), .oX_Cont(X_Cont), .oY_Cont(Y_Cont), .oFrame_Cont(Frame_Cont), .iDATA(rCCD_DATA), .iFVAL(rCCD_FVAL), .iLVAL(rCCD_LVAL), .iSTART(!KEY), .iEND(!KEY), .iCLK(CCD_PIXCLK), .iRST(DLY_RST_2) ); RAW2RGB u4 ( .iCLK(CCD_PIXCLK), .iRST(DLY_RST_1), .iDATA(mCCD_DATA), .iDVAL(mCCD_DVAL), .oRed(sCCD_R), .oGreen(sCCD_G), .oBlue(sCCD_B), .oDVAL(sCCD_DVAL), .iX_Cont(X_Cont), .iY_Cont(Y_Cont) ); wire cinza; RGB2GRAY u9 ( .clk (CCD_PIXCLK), .val (sCCD_DVAL), .iRED(sCCD_R) , .iBLUE(sCCD_B) , .iGREEN({sCCD_G,sCCD_G}), .oGRAY(cinza) ); SEG7_LUT_8 u5 ( .oSEG0(HEX0),.oSEG1(HEX1), .oSEG2(HEX2),.oSEG3(HEX3), .oSEG4(HEX4),.oSEG5(HEX5), .oSEG6(HEX6),.oSEG7(HEX7), .iDIG(Frame_Cont) ); sdram_pll u6 ( .inclk0(CLOCK_50), .c0(sdram_ctrl_clk), .c1(DRAM_CLK) ); assign CCD_MCLK = rClk; //AQUI ENTRAM 10BITS VERDE,VERMELHO E AZUL Sdram_Control_4Port u7 ( // HOST Side .REF_CLK(CLOCK_50), .RESET_N(1'b1), .CLK(sdram_ctrl_clk), // FIFO Write Side 1 .WR1_DATA({1'b0,cinza,cinza}), .WR1(sCCD_DVAL), .WR1_ADDR(0), .WR1_MAX_ADDR(640*480), .WR1_LENGTH(9'h100), .WR1_LOAD(!DLY_RST_0), .WR1_CLK(~CCD_PIXCLK), // FIFO Write Side 2 .WR2_DATA( {1'b0,cinza,cinza}), .WR2(sCCD_DVAL), .WR2_ADDR(22'h100000), .WR2_MAX_ADDR(22'h100000+640*480), .WR2_LENGTH(9'h100), .WR2_LOAD(!DLY_RST_0), .WR2_CLK(~CCD_PIXCLK), // FIFO Read Side 1 .RD1_DATA(Read_DATA1), .RD1(Read), .RD1_ADDR(0), .RD1_MAX_ADDR(640*480), .RD1_LENGTH(9'h100), .RD1_LOAD(!DLY_RST_0), .RD1_CLK(~VGA_CTRL_CLK), // FIFO Read Side 2 .RD2_DATA(Read_DATA2), .RD2(Read), .RD2_ADDR(22'h100000), .RD2_MAX_ADDR(22'h100000+640*480), .RD2_LENGTH(9'h100), .RD2_LOAD(!DLY_RST_0), .RD2_CLK(~VGA_CTRL_CLK), // SDRAM Side .SA(DRAM_ADDR), .BA({DRAM_BA_1,DRAM_BA_0}), .CS_N(DRAM_CS_N), .CKE(DRAM_CKE), .RAS_N(DRAM_RAS_N), .CAS_N(DRAM_CAS_N), .WE_N(DRAM_WE_N), .DQ(DRAM_DQ), .DQM({DRAM_UDQM,DRAM_LDQM}) ); assign UART_TXD = UART_RXD; I2C_CCD_Config u8 ( // Host Side .iCLK(CLOCK_50), .iRST_N(DLY_RST_2), .iZOOM_MODE_SW(SW), .iEXPOSURE_ADJ(KEY), .iEXPOSURE_DEC_p(SW), // I2C Side .I2C_SCLK(GPIO_1), .I2C_SDAT(GPIO_1) ); endmodule

[Altera_Forum]

Have you managed to get a frame out of it??

[Altera_Forum]

Hi everyone! 

I'm using the Terasic D5M camera along with the DE0 board. I also want to convert RGB to grayscale. If I were to use the sample code above (module RGBtoY), from which module output would the RGB come from?   What I mean to say is, would I use the outputs from the RAW2RGB module, as inputs to the RGBtoY module, and thus feed my output "Y" into the FIFO? Or would I use the outputs from the FIFO as inputs to the RGBtoY module?  I'm really new to this, and am pretty confused, so if anyone could provide me with some guidance it would be greatly appreciated! :)  Thanks, Tiffany

[Altera_Forum]

--- Quote Start ---  Hi everyone! I'm using the Terasic D5M camera along with the DE0 board. I also want to convert RGB to grayscale. If I were to use the sample code above (module RGBtoY), from which module output would the RGB come from?   What I mean to say is, would I use the outputs from the RAW2RGB module, as inputs to the RGBtoY module, and thus feed my output "Y" into the FIFO? Or would I use the outputs from the FIFO as inputs to the RGBtoY module?  I'm really new to this, and am pretty confused, so if anyone could provide me with some guidance it would be greatly appreciated! :)  Thanks, Tiffany  --- Quote End ---     Please reply if you got solution for this issue ...

[Altera_Forum]

Hi 

is there anyone can help in Background subtraction ? i want to subtract human hand from background and then display it on monitor. i know, there is a method that subtract current frame from previous frame ,if bigger than threshold it is a foreground and then update the background. but i have problem when i convert this algorithm to verilog code. pls help me if you know how to do this. i am using Altera DE2 with Terasic D5M

[Altera_Forum]

I am currently doing an image processing project in FPGA, and I am using TD5M, the same camera that you used when you posted that post about rgb2gray.  

Do you by any chance have sorted out how to do the rgb2gray conversion in vhdl/verilog? Do you have the source code?  The camera module only convert it to RGB, but my project require an output of greyscale, so I will need to create a rgb2gray in verilog and then integrate it with the existing module.   Thanks in advance.

[Altera_Forum]

Hi Tiffany, 

You just need to implement Gray=0.299*R + 0.587*G + 0.114*B equation in verilog, Multiplications can be done with simple shift operations. I have done this long back, couldn't locate the .v file. But implementation was straightforward, needs maximum 10 lines of coding.....  Feed the output from RAW2RGB into to your RGB2GRAY module... and then take the output(Y/Gray) in to the next processing unit. Y do u want to use a FIFO ?,  Cheers!! Fradaric              --- Quote Start ---  Hi everyone! I'm using the Terasic D5M camera along with the DE0 board. I also want to convert RGB to grayscale. If I were to use the sample code above (module RGBtoY), from which module output would the RGB come from?   What I mean to say is, would I use the outputs from the RAW2RGB module, as inputs to the RGBtoY module, and thus feed my output "Y" into the FIFO? Or would I use the outputs from the FIFO as inputs to the RGBtoY module?  I'm really new to this, and am pretty confused, so if anyone could provide me with some guidance it would be greatly appreciated! :)  Thanks, Tiffany  --- Quote End ---