HELP!! HOW TO WIRE 2 .vhd FILES!!!! IN QUARTUS!

[Altera_Forum]

Hey everybody  

   I have designed my own microprocessor (upro.vhd) in VHDL and my own(proper) memory(report) RAM of 256x4bits with QUARTUS II 9.0 (ram256x4.vhd), but I have a problem, I need to connect the DATA BUS and the ADDRESSES BUS of both files .vhd,    In the file up.vhd my ports are:   entity upro is  port (  clk: in std_logic; Rst: in std_logic; R_w: out std_logic; dir: out std_logic_vector (7 downto 0);  dat: inout std_logic_vector (3 downto 0) );  end upro;   . . . signal a: std_logic_vector(3 downto 0); signal carga_a: std_logic_vector(3 downto 0); signal pc: std_logic_vector(7 downto 0); signal carga_pc: std_logic_vector(7 downto 0); signal rdat_in: std_logic_vector(3 downto 0); signal dat_in: std_logic_vector(3 downto 0); signal dat_out: std_logic_vector(3 downto 0); signal rwaux: std_logic; signal presente: estado:= inicial;   ----------------------------------------------------- In the file ram256x4.vhd my ports are:   entity ram256x4 is  port (  Clock: in std_logic; OE: in std_logic; RW: in std_logic; CS: in std_logic; RW_Addr: in std_logic_vector (7 downto 0); Data_A: inout std_logic_vector (3 downto 0); Data_B: in std_logic_vector (3 downto 0); ); end ram256x4;   . . .  signal tmp_ram: ram_type;   What I need is to connect (like wire)the ports:   Clk -------- Clock  RW_Addr ---- dir  dat -------- DATA_A  RW --------- r_w    How can I do this wire connection in vhdl?   Somebody told my I need a new .vhd to call both .vhd archives using PORT MAP… BUT I DON’T KNOW HOW IT WORKS!

[Altera_Forum]

Hello, 

 If I understood, what you have to do is to instantiate your memory from the top file.   You can do it in this way:  entity upro is  port (  clk: in std_logic; Rst: in std_logic; R_w: out std_logic; dir: out std_logic_vector (7 downto 0);  dat: inout std_logic_vector (3 downto 0) );  end upro;   . . . signal a: std_logic_vector(3 downto 0); signal carga_a: std_logic_vector(3 downto 0); signal pc: std_logic_vector(7 downto 0); signal carga_pc: std_logic_vector(7 downto 0); signal rdat_in: std_logic_vector(3 downto 0); signal dat_in: std_logic_vector(3 downto 0); signal dat_out: std_logic_vector(3 downto 0); signal rwaux: std_logic; signal presente: estado:= inicial;  COMPONENT ram256x4 is  port (  Clock: in std_logic; OE: in std_logic; RW: in std_logic; CS: in std_logic; RW_Addr: in std_logic_vector (7 downto 0); Data_A: inout std_logic_vector (3 downto 0); Data_B: in std_logic_vector (3 downto 0); )  END COMPONENT;  ARCHITECTURE ...  BEGIN  TEST_ram256x4 : ram256x4  port map  (    Clock=>Clk,  RW_Addr=>dir, DATA_A =>dat, RW=>r_w, ...  );  ...  Hope it helps you  DABG  

[Altera_Forum]

Hey! thanks for your help, but what I want to know is how i can connect(wire) my 2 .vhd files!! I did what you answered to me but I got some mistakes. 

 I would like to share my information in this link, and also the password to your private mail in ALTERA FORUM!!! (and also for those who want to help me)    this is the link http://www.megaupload.com/?d=4z882uc9   thanks and I hope you understand me.

[Altera_Forum]

You can also connect both components by wire signals. But if no external signals are generated by them, they are simply discarded  

during Quartus synthesis. You have to use a VHDL simulator (e.g. ModelSim Altera Edition) to compile and simulate a design that  doesn't generate output signals.  Furthermore, I see that your RAM component has only inputs but no outputs. Something is obviously wrong with it.  If you want to show example designs, you should them upload as attachment with your posts.

[Altera_Forum]

hi!!! FvM 

 If you want I post A link, but I have already sent to you the files link and also the correct password, I have to lock the project because it is and academic proyect, so I need to develop it fine in order to share in my blog   I hope you could understand me.   Anpinilla89

[Altera_Forum]

hi 

 I apprecite any help I could recieve in this forum, remember that the pw is example1